Commit graph

19064 commits

Author SHA1 Message Date
Otavio Salvador
393ff47ba3 mxs: SPL: Generalize memory initialization
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-07 14:50:02 +01:00
Simon Glass
ac426b7290 x86: Fix coreboot config to boot on Chromebook
The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.

Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:45 -08:00
Gabe Black
d954a431ec x86: Turn on support for EFI's GPT in the coreboot config
This allows u-boot to figure out the partitions of a chrome-os install.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
cbca883c46 x86: coreboot: Enable video display
Enable the display on coreboot, using CFB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
058d59b08d x86: Build vga video code only if CONFIG_VIDEO_VGA is defined
When running from coreboot we don't want this code, so make it
optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
a94e9d70e3 x86: Remove video_init() prototype from u-boot-x86.h
This function is not intended to be exported from the video drivers, so
remove the prototype. This fixes an error:

cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Duncan Laurie
ae63057446 video: Check for valid FB pointer before clearing
This command will start erasing at memory address zero
if there is not a valid framebuffer address that was found
during video_init().

This is a common case with Chrome OS devices in normal mode
when we do not execute the video option rom in coreboot.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
c94663170b x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
2b9d2252aa x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
1350f1cce1 x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
7c71034d3c x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
b83058cd23 x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
488b8b242b x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Simon Glass
2712f08898 x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
ba74a0ffcb x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly
We will use coreboot.dtsi as our fdt include file.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
b208c7f1d0 x86: Add support for CONFIG_OF_CONTROL
Allow a device tree to be provided through the standard mechanisms.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Stefan Reinauer
05b71646a9 x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
91d82a29e7 x86: Add back cold- and warm-boot flags
These were removed, but actually are useful.

Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.

We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
112a575e49 x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.

Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
d65297b64d x86: Make calculate_relocation_address an overridable function
Different systems may have different mechanisms for picking a suitable place
to relocate U-Boot to.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
842d33874f x86: Make the upper bound on relocated symbols closed instead of open
This seems to be a bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
32f98735f9 x86: Reorder x86's post relocation memory layout
This changes the layout in decreasing addresses from:

1. Stack
2. Sections in the image
3. Heap

to

1. Sections in the image
2. Heap
3. Stack

This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
8313315b9a x86: Initialise SPI if enabled
If we have SPI support, make sure that we init it.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vic Yang <victoryang@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
ac31a7b81c x86: Implement arch_phys_memset so that it can wipe memory above 4GB
Implement arch_phys_memset so that it can set memory at physical addresses
above 4GB using PAE paging. Because there are only 5 page tables in PAE mode,
1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The
tables must be 4K page aligned and are declared that way, and because U-Boot
starts as 4K aligned and the relocation code relocates it to a 4K aligned
address, the tables work as intended.

While paging is turned on, all 4GB are identity mapped except for one 2MB
page which is used as the window into high memory. This way, U-Boot will
continue to work as expected when running code that expects to access memory
freely, but the code can still get at high memory through its window.

The window is put at 2MB so that it's 2MB page aligned, low in memory to be
out of the way of things U-Boot is likely to care about, and above the lowest
1MB where lots of random things live.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
40fef04906 Introduce arch_phys_memset which works like memset but on physical memory
The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Gabe Black
ec516c4899 x86: Increase the size of the phys_size_t and phys_addr_t types
These types should be 64 bits long to reflect the fact that physical
addresses and the size of physical areas of memory are more than 32 bits
long.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
0c3929092d x86: Fix off-by-one error in do_elf_reloc_fixups()
The use of post-increment with a do-while loop results in
the loop going one step too far when handling relocation fixups.

In about 1/100 cases this would cause it to hang.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
984d8b09fb x86: Ignore memory >4GB when parsing Coreboot tables
U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
34d6057be1 x86: Enable CONFIG_CMD_ZBOOT for coreboot
Enable this option to support booting a zImage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
1484311286 x86: Fix indirect jmp warning in zimage.c
This fixes the following warning:

zimage.c:312: Warning: indirect jmp without `*'

Also fixed these warnings to keep checkpatch quiet:

warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Stefan Reinauer
17de114f9f x86: Clean up MTRR 7 right before jumping to the kernel
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Graeme Russ
98568f0fa9 x86: Import MSR/MTRR code from Linux
Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
61e0ea900a x86: Provide a function to clean up just before booting a zimage
This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
095593c030 x86: Add basic cache operations
Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Gabe Black
9a7da182fa x86: Fill in the dram info using the e820 map on coreboot/x86
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
3cdc18a8de x86: Add a CBMEM timestamp generated right before the kernel startup.
To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
6dbe0cce3f x86: Enable coreboot timestamp facility support in u-boot.
This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Vadim Bendebury
2f899e03a9 x86: Add function to read time stamp counter
Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Bill Richardson
57be9172fc x86: gpio: Add additional GPIO banks to the ICH6 driver
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Simon Glass
a7e6d5496c x86: Enable ICH6 GPIO controller for coreboot
Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Bill Richardson
55ae10f8db x86: gpio: Add GPIO driver for Intel ICH6 and later.
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Luka Perkov
6e266bf88b add include/u-boot.lst to .gitignore
u-boot.lst is located in include directory. Update .gitignore file
accordingly.

Signed-off-by: Luka Perkov <luka@openwrt.org>
2012-12-06 13:56:39 -07:00
Robert P. J. Day
adb9d85139 README: Explain how to generate the CHANGELOG file.
Since the top-level README file refers the reader to the CHANGELOG,
it's worth mentioning how to generate it.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-06 13:56:39 -07:00
Robert P. J. Day
d4b901dd73 cmd_led.c: Standardize format of help and usage info.
Current "led" help and usage info has redundancy and extraneous
newlines, tweak it to be consistent with other commands.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-06 13:56:39 -07:00
Joe Hershberger
d060e6f441 Allow CONFIG_BOARD_SIZE_LIMIT to be specified in hex
Use the printf command to convert the number in any valid format into
the expected decimal format.  The resulting errors should be printed to
stderr.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-12-06 13:56:39 -07:00
Jerry Huang
33699df12c part: check each variable for capability calculation
In order to calculate the capability, we use the below expression to check:
((dev_desc->lba * dev_desc->blksz)>0L)
If the capability is greater than 4GB (e.g. 8GB = 8 * 1024 * 104 * 1024),
the result will overflow, the low 32bit may be zero.

Therefore, change to check each variable to fix this potential issue.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
2012-12-06 13:56:39 -07:00
Simon Glass
e3ff797cdb cbfs: Add docbook template
This adds a docbook template for fs, and makes CBFS use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 13:56:39 -07:00
Simon Glass
2592075776 cbfs: Remove mention of CREDITS files
As requested by Wolfgang, remove references to CREDITS in the CBFS
files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 13:56:38 -07:00
Stefan Reinauer
5fe8380db3 lzma: update to lzma sdk 9.20
Updated code taken from latest lzma sdk release 9.20 at
http://downloads.sourceforge.net/sevenzip/lzma920.tar.bz2

This generates quite a lot of checkpatch warnings, but I guess we
need to keep the code style as is to avoid a massive job each time we
update this.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 13:56:38 -07:00