Commit graph

50653 commits

Author SHA1 Message Date
Hou Zhiqiang
d170aca1a0 pci: layerscape: enable PCIe config ready
In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:06:11 -07:00
Udit Agarwal
ac55dadb1c fsl: Secure Boot: Enable IE (Key extention) Feature
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.

For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.

Following are the steps describing usage of this feature:

1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
   images stored in a static global structure.)
3) Use keys from IE table, to verify further images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:03:04 -07:00
Santan Kumar
6d7b9e78f5 armv8: ls2080ardb, ls2080aqds: Add mcmemsize in default env setting
Initialize mcmemsize to 0x40000000

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:01:44 -07:00
Hou Zhiqiang
9e052d9750 fsl-layerscape/ppa: cleanup ppa.h
Moved the ifdef into ppa.h and removed the duplicated macros.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:59:47 -07:00
Udit Agarwal
a8c6fd4ec1 armv8: LS2080A: Move sec_init to board_init
Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:58:46 -07:00
Udit Agarwal
350e16cfb4 armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080A
Add header address for PPA to be validated during ESBC phase for LS2080A
platform based on Layescape Chasis 3.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:56:33 -07:00
Lukasz Majewski
e46f8a3309 i2c: Set default I2C bus number
This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc)
without the need to first select the bus number with e.g. "i2c dev 0".

This is the "i2c" command behavior similar to the one from pre DM, where
by default bus 0 was immediately accessible.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:54 +02:00
Lukasz Majewski
b52a3fa08b i2c: ti: Update method to calculate psc, sscl and ssch I2C parameters
This patch updates the way in which psc, sscl and ssch I2C parameters are
calculated to be in sync with v4.9 Linux kernel
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c

The previous method was causing several issues:
- The internal I2C frequency (after prescaler) was far above recommended
one (7 - 12 MHz [*]) - the current approach brings better noise suppression
(as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb)

- The values calculated (psc, sscl and ssch) were far from optimal, which
caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast
Mode) of ~1.0us (the standard requires > 1.3 us).

[*] for AM57xx TRM SPRUHZ6G, Table 24,7
"HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes"

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:42 +02:00
Lukasz Majewski
e530d2e15b i2c: ti: Update SCLH and SCLL to be in sync with v4.9 Linux kernel
v4.9 Linux release:
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c

recommends to use SCLH=5 and SCLL=7 values.
This patch sets them to default.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:33 +02:00
Liam Beguin
0f5b461b9b i2c: lpc32xx: Force consistent bus numbering
Normally, this would probably be done by adding devicetree aliases
to the main dtsi file for the lpc32xx and using bus->req_seq instead.

Since we want to have consistent i2c numbering, we cannot force the
bus->req_seq because. If for instance we have 3 buses numbered
from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled;
i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands
because a bus can be probed using req_seq or seq interchangeably.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:20 +02:00
Liam Beguin
fb05788013 i2c: lpc32xx: Move definitions to header file
Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:14 +02:00
Sylvain Lemieux
ddfd082169 i2c: lpc32xx: Remove note for DM conversation
Removed note in the LPC32xx I2C driver for DM conversation.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:08 +02:00
Liam Beguin
d61c7adbff i2c: lpc32xx: Add DM for lpc32xx I2C
Adding DM specific wrapper functions and definitions.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:39 +02:00
Liam Beguin
eddac8e9fe i2c: lpc32xx: Factor out i2c_adapter parameter
This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:30 +02:00
Liam Beguin
552531e45d i2c: lpc32xx: Prepare compatibility functions
This is part of the prep work for the migration to the driver model.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:16 +02:00
Liam Beguin
03d924ae76 i2c: lpc32xx: Rename probe function
This is part of the prep work for the migration to the driver model.
What used to be the probe function is now called probe_chip.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:06 +02:00
Felix Brack
44d5c371a6 Add single register pin controller driver
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack <fb@ltec.ch>
2017-03-26 13:23:42 -06:00
Patrice Chotard
584861ffeb reset: Add STi reset support
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device.

Driver code has been mainly extracted from kernel
drivers/reset/sti/reset-stih407.c

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-26 13:22:58 -06:00
Hou Zhiqiang
0367bd4d60 pci: correct a function description
In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-03-26 13:22:58 -06:00
mario.six@gdsys.cc
3d1df0e363 lib: tpm: Add command to list resources
It is sometimes convenient to know how many and/or which resources are
currently loaded into a TPG, e.g. to test is a flush operation succeeded.

Hence, we add a command that lists the resources of a given type currently
loaded into the TPM.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26 13:22:58 -06:00
mario.six@gdsys.cc
1c08b210a8 cmd: tpm: Fix flush command
Commit 7690be35de ("lib: tpm: Add command to flush resources") added a command
to flush resources from a TPM.

However, a previous development version was accidentially used to generate the
patch, resulting in a non-functional command.

This patch fixes the flush command.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26 13:22:58 -06:00
mario.six@gdsys.cc
0f4b2ba176 tpm: Add function to load keys via their parent's SHA1 hash
If we want to load a key into a TPM, we need to know the designated parent
key's handle, so that the TPM is able to insert the key at the correct place in
the key hierarchy.

However, if we want to load a key whose designated parent key we also
previously loaded ourselves, we first need to memorize this parent key's handle
(since the handles for the key are chosen at random when they are inserted into
the TPM). If we are, however, unable to do so, for example if the parent key is
loaded into the TPM during production, and its child key during the actual
boot, we must find a different mechanism to identify the parent key.

To solve this problem, we add a function that allows U-Boot to load a key into
the TPM using their designated parent key's SHA1 hash, and the corresponding
auth data.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26 13:22:58 -06:00
Vignesh R
5efa1bfbfa libfdt: use CONFIG_IS_ENABLED for OF_LIBFDT
Use CONFIG_IS_ENABLED() macro to check whether OF_TRANSLATE is enabled, so
that code block is compiled irrespective of SPL or U-Boot build
and fdt address translation is used.

Signed-off-by: Vignesh R <vigneshr@ti.com>
2017-03-26 13:22:58 -06:00
James Balean
27cb7300ff Ensure device tree DTS is compiled
Enables custom DTS files, or those not associated with a specific target, to be compiled into a boot image.

Signed-off-by: James Balean <james@balean.com.au>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Simon Glass <sjg@chromium.org>
2017-03-26 13:22:58 -06:00
Hannes Schmelzer
db40c1aa1c drivers/net/phy: add fixed-phy / fixed-link support
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).

For this purpose we introduce a new phy-driver, called "Fixed PHY".

Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.

Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).

During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-03-26 09:58:26 -05:00
Tuomas Tynkkynen
f8e57c650d fdt_support: Fixup 'ethernet' aliases not ending in digits
The Raspberry Pi device tree files since Linux v4.9 have a "ethernet"
alias pointing to the on-board Ethernet device node. However,
U-Boot's fdt_fixup_ethernet() only looks at ethernet aliases ending
in digits.

As the spec doesn't mandate that aliases must end in numbers and there
have been much older uses of an "ethernet" aliases in the wild
(according to Tom Rini), change the code to accept "ethernet" as well.

Without this Linux isn't told of the MAC address provided by the
RPI firmware and the ethernet interface is always assigned a random MAC
address.

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:58:23 -05:00
Alexandre Messier
27a0f038a7 net: link_local: Fix netmask endianness bug
The network mask must be stored in network order when in a
'struct in_addr'.

This fix removes the "gatewayip needed but not set" message on the
console when using a link-local IP setup.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:58:19 -05:00
Suji Velupillai
5c624b9e9c net: fix cache misaligned issue in Broadcom SF2 driver
Fixed cache misaligned issue in the net driver. The issue shows-up when
a call to flush_dcache_range is made with unaligned memory. The memory
must be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Shamez Kurji <shamez.kurji@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>

Cover Letter:
This series resolves issues specific to the Broadcom SF2 driver:
- fix cache misaligned issue
- convert to Kconfig
END
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:58:15 -05:00
Yung-Ching LIN
ec7aa8fd67 board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
2017-03-26 09:58:11 -05:00
Yung-Ching LIN
d42db168e6 board: ge: bx50v3: fix AR8033 reset timing issue
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet

Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
2017-03-26 09:58:08 -05:00
oliver@schinagl.nl
625cf507ff net: sunxi: Enable eeprom on OLinuXino Lime boards
This patch enables the I2C EEPROM to be probed for a MAC address on the
OLinuXino Lime1 and Lime2 boards. Other boards surely qualify as well
but were not tested yet.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2017-03-26 09:57:55 -05:00
oliver@schinagl.nl
ace1520cb5 net: sunxi-emac: Write HW address via function
Currently the mac address is programmed directly in _sunxi_emac_eth_init
making it a one time inflexible operation. By moving it into a separate
function, we can now use this more flexibly.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:40:57 -05:00
Jagan Teki
a2f8a45696 configs: imx6: Select missing BOARD_LATE_INIT
Select missing BOARD_LATE_INIT from configs/ to
respective targets on arch area for Engicam imx6 boards.

Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-03-26 11:05:57 +02:00
Tim Harvey
d3a2bcf741 imx: ventana: add new board configs to MAINTAINERS
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2017-03-26 11:05:52 +02:00
Tim Harvey
d576d6f31c imx: ventana: fix GW5903 VDD_ARM rail
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2017-03-26 11:05:39 +02:00
Tom Rini
5cf618ee60 Merge git://git.denx.de/u-boot-arc
This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.
2017-03-24 08:19:30 -04:00
Vlad Zakharov
3daa7c7b83 arc: use timer driver for ARC boards
This commit replaces legacy timer code with usage of arc timer
driver.

It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.

Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24 14:47:52 +03:00
Vlad Zakharov
0c77092e81 arc: dts: separate single axs10x.dts file
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24 14:47:52 +03:00
Tom Rini
c1daa40773 Merge git://www.denx.de/git/u-boot-marvell
This mainly adds support for some new boards, like the ARMv8 community
boards MACCHIATOBin and ESPRESSBin
2017-03-24 07:21:57 -04:00
Vlad Zakharov
ad9b5f77df drivers: timer: Introduce ARC timer driver
This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-24 14:20:55 +03:00
Tom Rini
d0ffda8ed2 Merge git://git.denx.de/u-boot-dm 2017-03-23 12:19:07 -04:00
Dirk Eibach
60083261a1 arm: mvebu: Add gdsys ControlCenter-Compact board
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 15:48:28 +01:00
mario.six@gdsys.cc
2a792753d6 dm: Add callback to modify the device tree
Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.

The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.

Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.

Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 15:46:23 +01:00
Stefan Roese
1ec2a80b10 arm: mvebu: theadorable: Add 'pcie' test command
This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.

Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 10:52:28 +01:00
Stefan Roese
1304f4bb8e arm: mvebu: theadorable: Add board-specific PEX detection pulse width
Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).

In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 10:52:28 +01:00
Stefan Roese
2399e40120 arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width
Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.

Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 10:52:28 +01:00
Konstantin Porotchkin
d71e24950e arm64: a37xx: Remove DM_I2C_COMPAT from the board config
Remove DM_I2C_COMPAT from the board configurations for
Armada 37xx platform boards for supressing the buid tim
warning.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Konstantin Porotchkin
9566268fd8 arm64: a37xx: Disable DB configurations on ESPRESSOBin board
Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Konstantin Porotchkin
7c3105b5dd arm64: mvebu: Add default config for ESPRESSOBin board
Add initial default configuration for Marvell ESPRESSOBin
community board based on Aramda-3720 SoC

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Konstantin Porotchkin
d1625a9d19 arm64: dts: Add device tree for ESPRESSOBin board
Initial DTS file for Marvell ESPRESSOBin comunity board
based on Armada-3720 SoC.
The Marvell ESPRESSOBin is a tiny board made by Globalscale
and available on KickStarter site. It has dual core Armv8
Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM,
mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0
interfaces, Gigabit Ethernet switch with 3 ports, micro-SD
socket and two 46-pin GPIO connectors.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00