Commit graph

3 commits

Author SHA1 Message Date
Neal Frager
6be41ea4e6 arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)
  - DP system time clock PLL should use RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
67bf888850 arm64: zynqmp: Switch SOM to shared psu configuration
Previous psu init was targeting SOM + KV260 carrier card and also contain
configurations for other devices on carrier card. This config is removing
all expected configurations for CC and let U-Boot to handle all of it self.
This configuration is designed for SOM itself (and I would bet without
eMMC).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5782131058dc372befd3fdb4dceabeea5ba56606.1637236693.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
02ac1553b8 arm64: zynqmp: Add psu_init_gpl for k26 boards
Add psu_init_gpl file for getting SPL to work directly from the tree.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00