Commit graph

517 commits

Author SHA1 Message Date
huang lin
be1d5e0388 rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
2015-12-01 08:07:22 -07:00
huang lin
53c45f0ca2 rockchip: add rk3036 sdram driver
add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
07d8d35a61 rockchip: add early uart driver
add early uart driver so we can print debug message in
SPL stage

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
0b374c8dc8 rockchip: rk3036: Add a simple syscon driver
Add a driver that provides access to system controllers

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
2bc00e016e rockchip: rk3036: Add Soc reset driver
We can reset the Soc using some CRU (clock/reset unit) register.
Add support for this.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
302d1767b9 rockchip: add config decide whether to build common.c
some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
5138337b3f rockchip: rename board-spl.c to rk3288-board-spl.c
since different rockchip soc need different spl file,
so rename board-spl.c.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
8117803430 rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
cc2244b8fa rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Thomas Chou
98a51fc3d7 ns16550: unify serial_rockchip
Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:15 -05:00
Sjoerd Simons
b1f492ca9e rockchip: Reconfigure the malloc based to point to system memory
When malloc_base initially gets setup in the SPL it is based on the
current (early) stack pointer, which for rockchip is pointing into SRAM.
This means simple memory allocations happen in SRAM space, which is
somewhat unfortunate. Specifically a bounce buffer for the mmc allocated
in SRAM space seems to cause the mmc engine to stall/fail causing
timeouts and a failure to load the main u-boot image.

To resolve this, reconfigure the malloc_base to start at the relocated
stack pointer after DRAM  has been setup.

For reference, things did work fine on rockchip before 596380db was
merged to fix memalign_simple due to a combination of rockchip SDRAM
starting at address 0 and the dw_mmc driver not checking errors from
bounce_buffer_start. As a result, when a bounce buffer needed to be
allocated mem_align simple would fail and return NULL. The mmc driver
ignored the error and happily continued with the bounce buffer address
being set to 0, which just happened to work fine..

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-03 10:24:33 -06:00
Simon Glass
e2e947ff6b rockchip: Add basic support for jerry
This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
17aa548ced rockchip: Add basic support for firefly-rk3288
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
2444dae587 rockchip: Add core SoC start-up code
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
5ff093ab9e rockchip: rk3288: Add SDRAM init
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
13d80ff5af rockchip: rk3288: Add a simple syscon driver
Add a driver that provides access to system controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
3c5d0e34f6 rockchip: rk3288: Add SoC reset driver
We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00