Commit graph

495 commits

Author SHA1 Message Date
Bin Meng
510e379c49 riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:37 +08:00
Bin Meng
4694c93fef riscv: ae350: Clean up mixed tabs and spaces in the dts
There are quite a lot of mixed tabs and spaces in the ae350.dts.
Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:19 +08:00
Bin Meng
b5369c5813 riscv: Make start.S available for all targets
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:14 +08:00
Bin Meng
ed49ba4dcc riscv: bootm: Pass mhartid CSR value to kernel
So far this is hardcoded to zero, and we should read the value from
mhartid CSR and pass it to Linux kernel.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:08 +08:00
Bin Meng
e5ea1e5860 riscv: Remove CSR read/write defines in encoding.h
There is no reason to keep two versions of CSR read/write defines
in encoding.h. We already have one set of defines in csr.h, which
is from Linux kernel, and let's drop the one in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:02 +08:00
Bin Meng
2fab2e9c88 riscv: Add a helper routine to print CPU information
This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:55 +08:00
Bin Meng
ce7a8e0740 riscv: Explicitly pass -march and -mabi to the compiler
At present the compiler flag against which architecture and abi
variant the riscv image is built for is not explicitly indicated
which means the default compiler configuration is used. But this
does not work if we want to build a different target (eg: 32-bit
riscv images using a toolchain configured for 64-bit riscv).

Fix this by explicitly passing -march and -mabi to the compiler.
Since generically we don't use floating point in U-Boot, specify
the RV[32|64]IMA ISA and software floating ABI.

This also fix some alignment coding style issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:43 +08:00
Bin Meng
3d6015651b riscv: Fix coding style issues in the linker script
There are several coding style issues in the linker script. Fix them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:37 +08:00
Bin Meng
dfb828ed1c riscv: Move the linker script to the CPU root directory
The linker script can be shared by all RISC-V targets. Move it to
a common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:31 +08:00
Bin Meng
8cdc6b58d7 riscv: Remove mach type
Since the mach_id is not used by RISC-V, remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:19 +08:00
Bin Meng
4afeedf172 riscv: bootm: Correct the 1st kernel argument to hart id
The first argument of Linux kernel is the risc-v core hart id,
from which the kernel is booted from. It is not the mach_id,
which seems to be copied from arm.

While we are here, this also changes the Linux kernel entry
parameters' type to support both 32-bit and 64-bit.

Note the hart id is hardcoded to zero for now, and we should
change to fill in it with the value read from mhartid CSR of
the hart which this routine is currently running on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:46:51 +08:00
Bin Meng
3ad4866dd7 riscv: Remove setup.h
This was copied from ARM, and does not apply to RISC-V. While we
are here, bootm.h is eventually removed as its content is only
the inclusion of setup.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:44:44 +08:00
Bin Meng
117a433d9e riscv: kconfig: Normalize architecture name spelling
It's RISC-V that is the official name, not RISCV.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:44:38 +08:00
Bin Meng
d8d81d4a5d config.mk: Remove duplicated -fno-strict-aliasing
Now that we already disable the "strict-aliasing" globally, remove
the duplicates in the nds32/riscv/x86 arch-specific Makefiles.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-25 21:50:34 -04:00
Masahiro Yamada
3747bdbb2b arch: types.h: factor out fixed width typedefs to int-ll64.h
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.

Factor out the duplicated code into <asm-generic/int-ll64.h>.

BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Alexander Graf
122347f366 riscv: Include bss subsections in linker script
When we build with -fdata-sections we may end up with bss subsections. Our
linker script explicitly lists only a single consecutive bss section though.

Adapt the statement to also include subsections.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-20 14:25:59 +02:00
Alexander Graf
7e21fbca26 efi_loader: Rename sections to allow for implicit data
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.

In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".

Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.

With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.

Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
2018-07-25 14:57:44 +02:00
Ivan Gorinov
b71bb87af9 riscv: Remove unused _relocate arguments
EFI image handle and system table are not used in _relocate().

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
2018-07-19 16:31:37 -04:00
Rick Chen
7286e46a79 riscv: dts: Support cfi flash
Add nor node for cfi-flash driver and smc node
for smc(aftsmc020) controller.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:45:04 +08:00
Rick Chen
c14e90e844 riscv: dts: Sync DT with Linux Kernel
Use same dts to boot U-Boot and RISC-V
Linux Kernel v4.16-rc2 in ax25-ae350 platform.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:45:03 +08:00
Rick Chen
6f4dd62f33 riscv: cpu: nx25: Rename as ax25
Andes has rearranged the product combinations.
nx25 and ax25 both are RISC-V architecture cpu core.
But ax25 has MMU unit inside, and nx25 is not.

Cpu nx25 and platform ae250 are arranged in pairs.
Cpu ax25 and platform ae350 are arranged in pairs.

This patch will rename
nx25 as ax25
ae250 as ae350
nx25-ae250 as ax25-ae350
including filename, variable, string and definition.

Then u-boot can boot linux kernel in ae350
platform reasonably.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:45:02 +08:00
Rick Chen
7215787c4e SPDX: Convert single license tags to Linux Kernel style
Fix license tags problem after apply patchs about
riscv: Enable efi_loader support.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:44:21 +08:00
Rick Chen
6836adbe75 efi_loader: Enable RISC-V support
We have almost all pieces needed to support RISC-V UEFI binaries in place already.
The only missing piece are ELF relocations for runtime code and
data.

This patch adds respective support in the linker script and the runtime
relocation code. It also allows users to enable the EFI_LOADER configuration
switch on RISC-V platforms.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
b66babda45 riscv: Add board_quiesce_devices stub
This patch adds an empty stub for board_quiesce_devices() which allows boards
to quiesce their devices before we boot into an OS in a platform agnostic way.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
493d1e88b6 riscv: Add EFI application infrastructure
The hello world binary and a few selftests require to build EFI target
binaries, not just the EFI host environment.

This patch adds all required files to generate an EFI binary for
RISC-V.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
6cc1a2af46 riscv: Enable function sections
The linker can remove sections that are never addressed, so it makes a lot
of sense to declare every function as an individual section.

This reduces the output U-Boot code size by ~30kb for me.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
a7f99e5dd7 riscv: Add setjmp/longjmp code
To support efi_loader we need to have platform support for setjmp/longjmp.
Add it here.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Bryan O'Donoghue
accdce5f86 riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
820cba2ce8 riscv: Define PLATFORM__SET_BIT for generic_set_bit()
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Rick Chen
d58717e425 riscv: ae250: Support DT provided by the board at runtime
Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.

There are two methods to delivery dtb.
 1 Pass from loader:
   When u-boot boot from RAM, gdb or loader can pass dtb
   via a2 to u-boot dynamically. Of course gdb or loader
   shall be in charge of dtb delivery.

 2 Configure CONFIG_SYS_FDT_BASE:
   It can be configured as RAM or ROM base statically,
   no mater u-boot boot from RAM or ROM.
   If it was configured as ROM base, dtb can be burned
   into ROM(spi flash) by spi driver.

Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-03-30 13:13:56 +08:00
Rick Chen
177c16c933 riscv: dts: AE250 support sd High-Speed mode
Enable High-Speed mode with cap-sd-highspeed in dts.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:34 +08:00
Rick Chen
22b7e6fbd3 riscv: bootm: Remove ATAGS
ATAGS is not supported and will be replaced
by DT in riscv-linux. So can be removed now.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:29 +08:00
Rick Chen
0462358b62 riscv: bootm: Support to boot riscv-linux
riscv-linux should use BBL (Berkeley bootloader) for
loading the Linux kernel.

U-Boot can play as FSBL(first stage bootloader)
to boot BBL and riscv-linux.

In BBL's init_first_hart(), it will pass dtb with a1.
So implement bootm to pass arguments to BBL correctly.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:29 +08:00
Rick Chen
22e8c0f02b riscv: checkpatch: Fix static const char * array declarations
It is reported by checkpatch.pl
WARNING: static const char * array
should probably be static const char * const

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:22 +08:00
Rick Chen
b9076495db riscv: checkpatch: Fix missing a blank line after declarations
It is reported by checkpatch.pl
WARNING: Missing a blank line after declarations.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:22 +08:00
Rick Chen
45fc937576 riscv: checkpatch: Fix alignment should match open parenthesis
It is reported by checkpatch.pl.
CHECK: Alignment should match open parenthesis

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:22 +08:00
Rick Chen
40717eb849 riscv: checkpatch: Fix use of volatile
It is reported by checkpatch.pl
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:22 +08:00
Rick Chen
bc0818a6a9 riscv: checkpatch: Fix Macro argument reuse
It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
2018-03-30 13:13:22 +08:00
Rick Chen
f94c44e51e riscv: Add Kconfig to support RISC-V
Add Kconfig and makefile for RISC-V
Also modify MAINTAINERS for it.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00
Rick Chen
6020faf62c riscv: nx25: include: Add header files to support RISC-V
Add header files for RISC-V.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12 08:05:12 -05:00
Rick Chen
039ed7c572 riscv: nx25: dts: Add AE250 dts to support RISC-V
AE250 is the Soc using NX25 cpu core base on RISC-V arch.
Details please see the doc/README.ae250.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12 08:05:12 -05:00
Rick Chen
8bbb2909cb riscv: nx25: lib: Add relative lib funcs to support RISC-V
Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00
Rick Chen
e8e39597a3 riscv: cpu: Add nx25 to support RISC-V
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00