With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.
By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.
This adds the base driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
In order to keep SPL code size below the 32Kb limit,
put under CONFIG_SPL_BUILD flag all unused code in SPL.
This is needed for stm32f7xx board which are using SPL.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In case "gpio-ranges" property is not present in device tree,
use default value for gpio_count and gpio_range.
This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a"
command didn't return any pin status due to the fact that both stm32 F7
and H7 board DT doesn't use the gpio-ranges property.
Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.
For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.
This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.
This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.
The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This patch adds GPIO support for the Mediatek MT7621 SoC, tested on
MT7688 (Gardena smart-gateway). The driver is loosly based on the
Linux kernel version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed checkpatch.pl warnings: Prefer 'unsigned int' to bare use of 'unsigned']
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds gpio get_function ops support.
This function reports the state of a gpio.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The pca953x_gpio driver uses default value of polarity inversion
register. For some devices like PCA9557 and MAX7310, their polarity
inversion register default value is 0xf0. So for high 4 ports, when
reading their values, the values are inverted as the actual level.
This patch clears the polarity inversion register to 0 at init, so
that the port read and write values are aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Commit fb01e07a95 accidentally broke initialisation of GPIO
descriptor flags from device tree: currently the active low
flag from gpio-specifier is always ignored. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
Push generic defines of gpio.h out of mach-davinci to drivers/gpio
now that non-davinci architectures are beginning to use this IP.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix calimain build]
Signed-off-by: Tom Rini <trini@konsulko.com>
Change to use managed resource function devm_kcalloc(),
so it will auto free memory when driver is removed.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Enabled get_function support for dwapb where the function will
return the state of GPIO port.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Platforms with limited resources in SPL may enable OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The GPIO bank numbers do not appear in the device tree, so this
patch makes the gpio name based on the address
(ie gpio@49054000_31 vs gpio4_31)
adam
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
With DM and device tree support, let's use the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW from the device tree as they are intended.
Signed-off-by: Adam Ford <aford173@gmail.com>
The GPIO banks are broken up into two 16-bit registers for each
bank set. Unfortunately, the math that determines how to shift
blindly shifted by the number of the gpio. This worked for gpio
numbers under 32, but higher gpio's are broken. This fixes the
gpio index, so the bank is passed and the shift amount within
the register is passed now instead of the gpio number.
Fixes: 8e51c0f25406("dm: gpio: Add DM compatibility to
GPIO driver for Davinci")
Signed-off-by: Adam Ford <aford173@gmail.com>
Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).
Moreover this register if safe for simultaneous access by 2 master on
the bus.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
.set_value functions have no specified return value and gpio_uclass is
not working with it too. But this patch is returning 0 to be in sync
with others DM gpio drivers.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Reading registers for finding out output value is not working because
input value is read instead in case of tristate.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
There is no reason to do read/write for if/else separately.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Set a value before changing gpio direction. This will ensure that the
old value is not propagated when direction has changed but new value is
not written yet.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Call xilinx_gpio_get_bank_pin() before use.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
This patch used platdata structure instead of priv for storing static
information read from DT.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.
Example:
31 9 7 5 0 < bit number
| | | | |
[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
^ ^
| |
write 0x2 == set output to "1" (activate)
write 0x3 == set output to "0" (deactivate)
As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.
Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.
GPIO reset is handled via sysreset with adding this fragment to DT.
gpio-restart {
compatible = "gpio-restart";
gpios = <&reset_gpio 0 0 0>;
/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};
hard-reset-gpio property is not documented and also handled.
Conversion is required.
Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is enabling GPIO_DM support to have an option to use this
driver together with zynq gpio driver.
!DM part is kept there till Microblaze is cleanup which will be done
hopefully soon.
Just a note:
There is no reason to initialize uc-priv->name because it is completely
unused.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There should be proper bank name setup to distinguish between different
gpio drivers. Use dev->name for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove bogus zynq_gpio_getplat_data() and read driver data directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Relocate gpio ops as was done by:
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The omap_gpio driver has a TODO that says when every board is converted
to DM and DT, the omap_gpio_bind can stop using calloc and switch
to auto-alloc.
This patch converts this driver to auto-calloc when DT is enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
There are multiple GPIO banks with up to 32 pins / bank. When
using 'gpio status -a' to read the pins, this patch displays
both GPIO<bank>_<index> similar to how the device trees
display in addition to displaying gpio_#
Signed-off-by: Adam Ford <aford173@gmail.com>
