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7 commits

Author SHA1 Message Date
Chanho Park
30b0f58dc7 riscv: dts: jh7110: Add rng device tree node 
Adds jh7110 trng device tree node.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-11-02 17:45:53 +08:00
Torsten Duwe
6164d86984 riscv: jh7110: enable riscv,timer in the device tree 
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-09-05 10:53:36 +08:00
Mason Huo
8db2224ffc riscv: dts: starfive: Enable PCIe host controller 
Enable and add pinctrl configuration for PCIe host controller.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-08-02 11:02:32 +08:00
Xingyu Wu
6c4b50e6de riscv: dts: jh7110: Add clock source from PLL 
Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-24 13:21:06 +08:00
Xingyu Wu
005f9627d0 riscv: dts: jh7110: Add PLL clock controller node 
Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-24 13:21:01 +08:00
Yanhong Wang
55a2b82690 riscv: dts: jh7110: Add ethernet device tree nodes 
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-12 13:21:40 +08:00
Yanhong Wang
9087a6ae79 riscv: dts: jh7110: Add initial StarFive JH7110 device tree 
Add initial device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
 2023-04-20 16:08:45 +08:00