Commit graph

42 commits

Author SHA1 Message Date
Bernhard Messerklinger
0709ddb68f x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on Intel CrownBay and MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[bmeng: fix compiler warnings when building the driver for 64-bit]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Bin Meng
ab20107468 spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
d2ca80c3d7 x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
52dd56ba84 x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
b42711f90c x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
3e79141684 x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
7d82978927 x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
94bc9177ca x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Stefan Roese
4759dffe23 spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit
This patch adds a remove function to the Intel ICH SPI driver, that will
be called upon U-Boot exit, directly before the OS (Linux) is started.
This function takes care of configuring the BIOS registers in the SPI
controller (similar to what a "standard" BIOS or coreboot does), so that
the Linux MTD device driver is able to correctly read/write to the SPI
NOR chip. Without this, the chip is not detected at all.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
2017-05-17 17:13:06 +08:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Jagan Teki
08fe9c294f spi: Use mode for rx mode flags
Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Bin Meng
3e389d8ba6 dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
6e670b5c4d spi: ich: Change PCHV_ to ICHV_
The ICH SPI controller supports two variants, one of which is ICH7
compatible and the other is ICH9 compatible. Change 'pch_version'
to 'ich_version' to better match its original name.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
1f9eb59d27 spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
9eb4339ba4 spi: ich: Some clean up
This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-02-05 12:47:20 +08:00
Simon Glass
f2b85ab5e6 dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Simon Glass
fffe25db04 spi: ich: Separate out the read/write trace from normal debugging
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Jagan Teki
91292e0bee spi: Rename op_mode_rx to mode_rx
Since spi rx mode macro's are renamed to simple and
meaninfull, this patch will rename the respective
structure members.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13 18:47:26 +05:30
Jagan Teki
e5961f0706 spi: Rename SPI_OPM_RX_* to SPI_RX_*
SPI_OPM_RX_AS 	- SPI_RX_SLOW
SPI_OPM_RX_AF	- SPI_RX_FAST
SPI_OPM_RX_DOUT	- SPI_RX_DUAL
SPI_OPM_RX_QOF	- SPI_RX_QUAD

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13 18:47:26 +05:30
Jagan Teki
cdf3393814 spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUAD
Since SPI_TX_* are spi_slave{} members so use spi protocol
notation instead spi flash programming, like

SPI_TX_BP  => SPI_TX_BYTE
SPI_TX_QPP => SPI_TX_QUAD

Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13 18:47:25 +05:30
Jagan Teki
095a41d3c2 spi: Use mode instead of op_mode_tx
Used mode member from spi_slave{} instead of op_mode_tx.

Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13 18:47:25 +05:30
Tom Rini
446d37c1ac Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-10-28 16:56:43 -04:00
Jagan Teki
69fd4c386c spi: ich: Use BIT macro
Replace numerical bit shift with BIT macro
in ich

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:16 +05:30
Simon Glass
bcbe3d1579 dm: Rename dev_get_parentdata() to dev_get_parent_priv()
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-23 09:42:28 -06:00
George McCollister
5ac98cb9bd x86: spi: Add support for Wildcat Point
Add the Wildcat Point ID so Broadwell U based boards can use SPI.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:27 -06:00
Simon Glass
5078792807 dm: spi: Correct BIOS protection logic for ICH9
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
2015-07-14 18:03:19 -06:00
Simon Glass
e1e332c8f2 dm: spi: Correct status register access width
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14 18:03:19 -06:00
Simon Glass
5d4a757ca5 dm: spi: Correct minor nits in ICH driver
Tidy up three minor problems in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14 18:03:15 -06:00
Simon Glass
ba4575626e dm: x86: spi: Convert ICH SPI driver to driver model
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
87108cf20a x86: spi: Add support for lynxpoint
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-16 19:27:40 -06:00
Bin Meng
728b393f3b x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Simon Glass
5093badbb5 x86: spi: Support ValleyView in ICH SPI driver
The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
8e899af059 x86: spi: Add device tree support
As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Bin Meng
7e7740397d x86: ich-spi: Add Intel Tunnel Creek SPI controller support
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
996467172e x86: ich-spi: Set the tx operation mode for ich 7
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
fa388bca3e x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
15c7c6b31a x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Simon Glass
5e6fb69778 x86: spi: Set maximum write size for ICH
This SPI controller can only write 64 bytes at a time. Add this restriction
in so that 'sf write' works correct for blocks larger than 64 bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
1853030e21 x86: spi: Add Intel ICH driver
This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.

This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00