Commit graph

5 commits

Author SHA1 Message Date
Dylan Hung
abc75897ca ARM: dts: ast2600: Add MDIO devices
There are 4 MDIO bus controllers in AST2600 SOC.  Each of them can
connect to one or more PHY chips and is flexible to work with the 4 MAC
devices in AST2600.  On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY
chips used by MAC 0,1,2,3 respectively.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Chia-Wei Wang
f05522749c ARM: dts: ast2600: Add ACRY to device tree
Add ACRY DTS node and enable it for AST2600 EVB.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:00 -05:00
Joel Stanley
a2f16d0073 ARM: dts: ast2600: Add HACE to device tree
Add HACE DTS node and enable it for AST2600 EVB.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
8e1ebdcfd7 ARM: dts: ast2600: Make WDT by default disabled
The WDT devices described in the general .dtsi file
should be marked as "disabled" by default.

A WDT should be then enabled in the board specific
.dts file on demands.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-10-03 11:59:22 -04:00
Chia-Wei, Wang
ec55a1df39 ARM: dts: aspeed: Add AST2600 SoC support
AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.

AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:23:06 -05:00