Commit graph

28355 commits

Author SHA1 Message Date
Siva Durga Prasad Paladugu
87f3dbdffc ARM: zynq: Enable DFU functionality in zynq
Enable DFU functionality in zynq.
This DFU functionality helps us to load linux
images on to DDR and can boot linux using bootm.
In order to load images the user should run dfu
command "dfu 0 ram 0" from u-boot prompt and then
send the images from host.

The malloc size has been increased to match the DFU
buffer requirements.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:58 +01:00
Siva Durga Prasad Paladugu
f20b37f353 ARM: zynq: provide config option to select emio
Dont send always emio value as zero for zynq_gem_initialize
send it based on config.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:58 +01:00
Michal Simek
dd1c351ffe ARM: zynq: Group ethernet configuration options together
No functional chagnes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:58 +01:00
Michal Simek
e9d69c1c71 ARM: zynq: Use CMD_FS_GENERIC
Based on:
"am335x_evm: Enable CMD_EXT4 and CMD_FS_GENERIC, add bootpart to env"
(sha1: 73a27a84e5)

Fix filesystem specific commands for loading.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:58 +01:00
Michal Simek
5a82d53c78 ARM: zynq: Show board information by default
Show board information in bootlog and enable it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
c8eac66bae ARM: zynq: List qspi, smc and nand baseaddresses
Add missing addresses to the list.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
63e3cea515 ARM: zynq: List nand, qspi and jtag boot modes
Use full boot mode list in SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Siva Durga Prasad Paladugu
f60c6fbbc6 ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
3ad87ca182 ARM: zynq: ddrc: Setup half of memory only for ECC case
Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
555c7c066f ARM: zynq: Remove empty line
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
c08cfc2d2c ARM: zynq: Enable the Neon instructions
Added the lowlevel_init to enable the Neon instructions.

Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.

Also enable neon instructions for non-xilinx toolchain.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:31 +01:00
Tom Rini
03cae7261e Merge branch 'master' of git://git.denx.de/u-boot-marvell 2015-01-25 19:05:40 -05:00
Gerald Kerma
361b3d8613 marvell: kirkwood: guruplug refresh for newer kernel
Refresh for newer kernel.
Prepare ENV settings for sheevaplugs to be OpenWRT ready.

    +----------+
    | UBOOT    | >> 896 Kb (7x128)  = uboot
    +----------+
    | ENV      | >> 128 Kb          = uboot_env
    +----------+
    | ROOT(FS) | >> 511 Mb @ 1 Mb   = root -> rootfs (ubifs)
    +----------+

With (CC) TRUNK OpenWRT build (QUICK HOWTO) :

    <INTERRUPT>
    Marvell>> nand erase.part root
    Marvell>> ubi part root
    Marvell>> ubi remove rootfs
    Marvell>> ubi create rootfs
    Marvell>> usb reset
    Marvell>> fatload usb 2:1 0x800000 guruplug/openwrt/openwrt-kirkwood-guruplug-rootfs.ubifs
    Marvell>> ubi write 0x800000 rootfs ${filesize}
    Marvell>> reset

Changes in v1:
- ADD generic board define
- ADD FDT support
- ADD HUSH interpreter
- Define new NAND partition mapping

Signed-off-by: Gerald Kerma <dreagle@doukki.net>
2015-01-26 00:25:29 +01:00
Luka Perkov
d4d8f1b726 kirkwood: sheevaplug: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
604a0dd64e kirkwood: pogo_e02: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
92ca8bda41 kirkwood: iconnect: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
15155b49ad kirkwood: goflexhome: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
6054b153a5 kirkwood: dockstar: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
c147ff9df1 kirkwood: ib62x0: add CONFIG_SYS_GENERIC_BOARD define
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
CC: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:16 +01:00
Luka Perkov
62d1e990d9 ARM: kirkwood: fix cpu info for 6282 device id
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-25 23:56:15 +01:00
Luka Perkov
5aa2297da7 kirkwood: define empty CONFIG_MVGBE_PORTS by default
Each board with defines it's own set of values. If we do not define
CONFIG_MVGBE_PORTS we will hit following error:

mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:700:34: error: 'CONFIG_MVGBE_PORTS' undeclared (first use in this function)
  u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;

This patch fixes above described problem.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2015-01-25 23:56:15 +01:00
Luka Perkov
49413ea3f5 cosmetic: kirkwood: style fixes in kwbimage.cfg files
When diffing through the changes only the relevant changes
should be displayed.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-25 23:56:09 +01:00
tang yuantian
41ba57d0c7 fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24 09:12:32 -06:00
Simon Glass
e43ade3749 x86: config: chromebook_link: Enable environment
Enable an environment area.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:46 -07:00
Simon Glass
380ab5cc27 x86: ivybridge: Drop the Kconfig MRC cache information
This is now stored in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:46 -07:00
Simon Glass
069f5481ba x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:45 -07:00
Simon Glass
191c008a21 x86: Implement a cache for Memory Reference Code parameters
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.

Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
a9aff2f46a x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
146251f87e Allow architecture-specific memory reservation
All memory to be reserved for use after relocation by adding a new call
to perform this reservation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
8e899af059 x86: spi: Add device tree support
As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
fc4860c089 x86: rtc: mc146818: Add helpers to read/write CMOS RAM
On x86 we use CMOS RAM to read and write some settings. Add basic support
for this, including access to registers 128-255.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:44 -07:00
Simon Glass
b18c68d891 x86: Use ipchecksum from net/
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:44 -07:00
Simon Glass
9b0e35cb48 net: Add a separate file for IP checksumming
Move the checksum code out into its own file so it can be used elsewhere.
Also use a new version which supports a length which is not a multiple of
2 and add a new function to add two checksums.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 21:44:59 -07:00
Simon Glass
5da38086bd x86: dts: Add compatible string for Intel ICH9 SPI controller
Add this to the enum so that we can use the various fdtdec functions. A
later commit will move this driver to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 21:44:59 -07:00
Alison Wang
55d53ab45e arm: ls102xa: Add LPUART support for LS1021ATWR board
This patch adds LPUART support for LS1021ATWR board.
For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:15 -06:00
Alison Wang
8fc2121a10 arm: ls102xa: Add LPUART support for LS1021AQDS board
This patch adds LPUART support for LS1021AQDS board.
For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:15 -06:00
Alison Wang
33d2e46591 ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Alison Wang
7df50fd323 arm: ls102xa: Update snoop settings for CCI-400
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
tang yuantian
5699274373 ARM: HYP/non-sec: Make variable gic_dist_addr as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Xiubo Li
dd04832d52 ls102xa: dcu: Add platform support for DCU on LS1021AQDS board
This patch adds the CH7301 HDMI options and the common configuration
for DCU on LS1021AQDS board.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Cc: Jason Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
0181937fa3 crypto/fsl: Add fixup for crypto node
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
d8f527578e arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROL
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>.  As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they
do not support GPIO.

The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h>
to support OF_CONTROL for LS102x platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Alison Wang
0f5e5579f2 ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
York Sun
dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:13 -06:00
Sjoerd Simons
053b86e6d8 pci: tegra: Fix port information parsing
commit a62e84d7b1 incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).

With this patch i can successfully network boot my jetson tk1

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2015-01-23 17:25:30 -07:00
Bin Meng
fea1c47f54 x86: Fix various code format issues in start16.S
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
3b621ccabd x86: Test mtrr support flag before accessing mtrr msr
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
4949166906 x86: Save mtrr support flag in global data
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
566d1754d3 x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Simon Glass
d1a5d3c133 x86: config: Always scroll the display by 5 lines, for speed
Scrolling a line at a time is very slow for reasons that I don't understand.
It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope
with this, scroll 5 lines each time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00