This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The symbol "_start" is defined twice in arch/arm/lib/vectors.S:
around line 48 and line 54.
If CONFIG_SYS_DV_NOR_BOOT_CFG is defined (as on calimain board),
build fails:
arch/arm/lib/vectors.S: Assembler messages:
arch/arm/lib/vectors.S:54: Error: symbol `_start' is already defined
make[1]: *** [arch/arm/lib/vectors.o] Error 1
make: *** [arch/arm/lib] Error 2
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Currently cntvoff_el2 is initialised with an arbitrary bag of bits
derived from the initial value of cnthctl_el2 on the current CPU. This is
somewhat odd and problematic as some of these bits are UNKNOWN at reset
and may differ across CPUs (which may cause an OS at EL1 to observe time
going backwards across CPUs).
This patch instead initialises cntvoff_el2 with xzr, giving the register
a consistent value of zero on all CPUs.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Tom Rini <trini@ti.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>
Add QSPI support for VF610TWR, such as clock and iomux.
Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher. Add a similar hook to start with.
Signed-off-by: Tom Rini <trini@ti.com>
For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.
Also the 'Timer register bits' are expanded.
By the way we add defines for all timers within AM335x SoC.
Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared. When SPL booting, this is handled by setting gd
to point to SRAM in s_init. However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.
Signed-off-by: Tom Rini <trini@ti.com>
We have two contexts for booting these platforms. One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads. The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.
In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus). In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.
Signed-off-by: Tom Rini <trini@ti.com>
The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.
Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.
Signed-off-by: Pekon Gupta <pekon@ti.com>
For each of Jetson TK1, Venice2, and Beaver:
- Enable the first USB controller in DT, and describe its configuration.
- Enable USB device/gadget support. This allows the user to type e.g.
"ums 0 mmc 0" at the command-line to cause U-Boot to act a USB device
implementing the USB Mass Storage protocol, and expose MMC device 0
that way.
This allows a host PC to mount the Tegra device's MMC, partition it, and
install a filesystem on it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.
Add a call in SPL to enable PSHOLD.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Now that the GPIO numbering series has been applied, we can use the correct
GPIO for the EC interrupt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Also we enable the mmc command in configuration file.
As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION,
so remove the redundant CONFIG_DOS_PARTITION definition.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
For sama5d3xek we need to modify the SPL image for correct detection by ROM
code.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
If without switch to main crystal oscillator, the sama5d3 SoC will
use internal on chip RC oscillator.
In order to get better accuracy, switch to main crystal oscillator.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add support for booting from an MMC card.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > + case 1:
> > +#if CONFIG_MMC1_PG
> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?
It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...
> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.
...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.
> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>
Thanks!
8<---------------------------------
>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support
This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: Tom Rini <trini@ti.com>
Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i)
processors. Enable for the Cubietruck.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.
Signed-off-by: Adam Sampson <ats@offog.org>
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
This patch adds the basic clocks and timer support for the Allwinner A20
(sun7i) processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
Some of the code here is common to multiple sunxi subarchtectures, hence files
are named sun4i which is the earliest similar variant.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
Signed-off-by: Stefan Agner <stefan@agner.ch>
As revision code 1 is for silicon revision 2.0, it is easily confused with
silicon revision 1.0.
Device type report also reworked in same style.
Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Last section of DMM is used for trapping tiler unmapped sections.
Corresponding trap_size should be deducted from total SDRAM size
only if trap section is overlapping with available SDRAM
based on DMM sections. Fixing the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The omap_hw_init_context function (and assorted helpers) is the same for
all OMAP-derived parts as when CHSETTINGS are used, that's the same and
our DDR base is also always the same. In order to make this common we
simply need to update the names of the define for DDR address space
which is also common.
Cc: Sricharan R. <r.sricharan@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
TPS65917 is used in DRA722 evm. Update the address offsets accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tom Rini <trini@ti.com>
GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
- Ethernet Devices like LAN9220
Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.
Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.c
However, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: arch/arm/include/asm/arch-omap3/mem.h
OMAP4: arch/arm/include/asm/arch-omap4/mem.h
OMAP4: arch/arm/include/asm/arch-omap5/mem.h
Also, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
CONFIG_NAND: initialize GPMC for NAND device
CONFIG_NOR: initialize GPMC for NOR device
CONFIG_ONENAND: initialize GPMC for ONENAND device
Signed-off-by: Pekon Gupta <pekon@ti.com>
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini <trini@ti.com>
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.
Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELM
Platform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects available
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.
Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELM
Platform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects available
Signed-off-by: Pekon Gupta <pekon@ti.com>
