Commit graph

163 commits

Author SHA1 Message Date
Simon Glass
24696e2f21 cros_ec: Remove the old tunnel code
This is not needed with driver mode. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
f48eaf01b2 cros_ec: Support the LDO access method used by spring
Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.

There are two implementation choices:

1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for retrying when the LDO fails to come up.

2. Write a special I2C bus driver which pretends to be a TPS65090 and
transfers reads and writes using the LDO message.

Either is distasteful. The latter method is chosen since it results in less
code duplication and a fairly simple (30-line) implementation of the core
logic.

The crosec 'ldo' subcommand could be removed (since i2c md/mw will work
instead) but is retained as a convenience.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:11 -06:00
Simon Glass
cc456bd7df dm: cros_ec: Convert the I2C tunnel code to use driver model
The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This
currently uses a copy of the I2C command code and a special 'crosec'
sub-command.

With driver model we can define an I2C bus which tunnels through to the EC,
and use the normal 'i2c' command to access it. This simplifies the code and
removes some duplication.

Add an I2C driver which tunnels through to the EC. Adjust the EC code to
support binding child devices so that it can be set up. Adjust the existing
I2C xfer function to fit driver model better.

For now the old code remains to allow things to still work. It will be
removed in a later patch once the new flow is fully enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:11 -06:00
Stefan Roese
f5df36d0c8 misc: led: pca9551_led: Fix problem with multiple blink frequencies
Only 2 frequencies are supported. The current driver implementation does
not always use the 2 last configured blink frequencies. This patch
fixes this problem. So that the last two entered frequencies are
active.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
2015-07-27 15:01:57 -04:00
Simon Glass
04035fd36c dm: test: Add a test for the system controller uclass
Add a test to confirm that we can access system controllers and find their
driver data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:33 -06:00
Simon Glass
5010d98f02 sandbox: Use the reset driver to handle reset
Move sandbox over to use the reset uclass for reset, instead of a direct
call to do_reset(). This allows us to add tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:31 -06:00
Simon Glass
b9d33fa06c sandbox: Add a warm and cold reset driver
Add drivers for sandbox. One can only perform a warm reset (which does
nothing). The other can perform a cold reset or a power reset (the
latter will quit U-Boot). These can be used for testing the reset uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:31 -06:00
Simon Glass
1704d083b3 dm: reset: Allow reset_walk() to return
Add a new reset_walk_halt() function to cause a reset and then halt on
failure. The reset_walk() function returns an error code.

This is needed for testing since otherwise U-Boot will halt in the middle
of a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:31 -06:00
Simon Glass
f9917454d5 dm: Add a system reset uclass
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.

To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:29 -06:00
Bhupesh Sharma
dbe94dd11c driver/fsl_debug_server: Fix the DDR hide logic for LS2085a
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
Simon Glass
b527924954 sandbox: cros_ec: Support EC_CMD_ENTERING_MODE emulation
Emualate this function which is used with Chrome OS verified boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-14 18:49:34 -06:00
Simon Glass
3806882042 sandbox: Add missing errno.h includes in a few files
These files use error numbering, so add the include.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-14 18:49:34 -06:00
Stefan Roese
1cdd941200 misc: led: Add PCA9551 LED driver
This patch adds a driver for the PCA9551 LED controller.

Originated-by: Timo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-05-08 17:24:17 -04:00
Simon Glass
527265d8f2 cros_ec: Handle the single duplex requirement in cros_ec
With several chips using the SPI protocol it seems better to put the single
duplex functionality in the EC rather than the SPI driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-05 20:58:19 -06:00
Simon Glass
c4b206dff1 cros_ec: Show the protocol version in the debug message
When starting up, show the protocol version that has been negotiated with
the EC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-05 20:58:18 -06:00
Bin Meng
19268834fb x86: Set serial port IRQ for SMSC LPC47M
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Tom Rini
3f6dcdb9cd Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-04-24 13:43:24 -04:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Prabhakar Kushwaha
45bc6fd108 driver/fsl_ifc: Add support to finalize CS1, CS3 address binding
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:52 -07:00
Stefan Roese
a8eeaf2f7a cmd_led: Extend led command to support blinking and more leds
This patch extends the U-Boot "led" command to support automatic blinking
by setting a blink frequency in milliseconds. Additionally the number of
supported LEDs is increased to 6 (0...5).

This will be used by the PCA9551 LED driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-04-23 09:43:08 -04:00
Bhupesh Sharma
422cb08acb armv8/fsl-lsch3: Add Freescale Debug Server driver
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:26:29 -07:00
Simon Glass
47cb8c654b sandbox: cros_ec: Add Kconfig for sandbox EC config
Move CONFIG_CROS_EC_SANDBOX to Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
3fbb78711c cros_ec: exynos: Match up device tree with kernel version
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.

For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
60f37fc6aa cros_ec: Drop unused CONFIG_DM_CROS_EC
Since all supported boards enable this option now, we can remove it along
with the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
e96fc7dfc8 cros_ec: Reinit the cros_ec device when 'crosec init' is used
This command is supposed to reinit the device. At present with driver
model is does nothing. Implement this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
72a38e06a2 dm: cros_ec: Convert cros_ec LPC driver to driver model
This is the last driver to be converted. It requires an LPC bus and a
special check_version() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
a33aca10ac dm: sandbox: pci: Enable PCI for sandbox
Enable PCI options so that sandbox can be used for testing this bus with
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:07 -06:00
Simon Glass
d2cb9b2b00 dm: sandbox: Add a emulated PCI device as an example
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:09:45 -06:00
Simon Glass
e564f054af dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:42 -06:00
gaurav rana
fe78378d7d fsl_sec_mon: Add driver for Security Monitor block of Freescale
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00
Simon Glass
6fb9ac15eb dm: cros_ec: Convert to Kconfig
Since both I2C and SPI are converted to Kconfig, we can convert cros_ec
to Kconfig for these buses.

LPC will need to wait until driver mode PCI is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-19 06:19:18 -07:00
Simon Glass
f94a1bed07 dm: Expand and complete Kconfig in drivers/
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-12 10:35:33 -07:00
Simon Glass
85df958ce2 dm: cros_ec: Convert cros_ec_i2c over to driver model
Move this driver to use driver model and update the snow configuration to
match.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:01 -07:00
Simon Glass
b2568f0d57 dm: cros_ec_spi: Remove old pre-driver-model code
This is no-longer needed since all platforms use SPI for cros_ec.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:57 -07:00
Simon Glass
8bbb38b15f dm: cros_ec: Don't require protocol 3 support
I2C is now deprecated on ARM platforms and there are no devices that use it
with the v3 protocol. We can't require v3 support if we want to support I2C.
Adjust the error handling to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:57 -07:00
Simon Glass
d0cff03e18 dm: spi: Move slave details to child platdata
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.

However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.

Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
32f8a19f6d dm: cros_ec: Remove use of fdtdec GPIO support
These functions are going away, so use the new uclass support instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:51 -07:00
Masahiro Yamada
ee5ee87642 i2c_eeprom: include <linux/err.h> to fix build error
drivers/misc/i2c_eeprom.c fails to build unless CONFIG_FIT_SIGNATURE
is defined.

  CC      drivers/misc/i2c_eeprom.o
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:15:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:15:10: note: each undeclared identifier
is reported only once for each function it appears in
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_write':
drivers/misc/i2c_eeprom.c:21:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:22:1: warning: control reaches end of
non-void function [-Wreturn-type]
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:16:1: warning: control reaches end of
non-void function [-Wreturn-type]
make[2]: *** [drivers/misc/i2c_eeprom.o] Error 1
make[1]: *** [drivers/misc] Error 2
make: *** [drivers] Error 2

By the way, Sandbox (enabling CONFIG_FIT_SIGNATURE) is luckily
working depending on it.
Sandbox includes include/asm-generic/errno.h
            from include/errno.h
            from include/u-boot/rsa-checksum.h
            from include/image.h
            from include/common.h
            from drivers/misc/i2c_eeprom.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:15 -07:00
Bin Meng
a2927e09bc x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Simon Glass
20142019a9 dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Fabio Estevam
a847fff11c mxc_ocotp: Do not disable the OCOTP clock after every access
Leave the OCOTP turned on, so that we subsequent access do not fail.

After enabling the thermal driver on a mx6sxsabresd board:

U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
CPU:   Temperature 48 C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
  00:01.0     - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller
In:    serial
Out:   serial
Err:   serial
Net:
(hang)

As the thermal driver accesses the ocotp registers, its clock will be disabled
afterwards.

Then when the MAC address is read (also from ocotp registers) it will cause a
hang.

Do not disable the ocotp clock to prevent this problem.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2014-12-01 10:20:19 +01:00
Hector Palacios
3d99fcbc15 mxs_ocotp: clear the error flag before initiating write operation
A previous operation may have set the error flag, which must be cleared
before a new write operation can be issued.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:42 +01:00
Hector Palacios
ad5dd7ae4b mxs_ocotp: check for errors from the OTP controller after writing
The write operation may fail when trying to write to a locked area. In
this case the ERROR bit is set in the CTRL register. Check for that
condition and return an error.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:19:41 +01:00
Hector Palacios
d8d160e420 mxs_ocotp: prevent error path from returning success
The code may goto 'fail' upon error with 'ret' variable set to an error
code, but this variable was being overwritten by a final preparation
function to restore the HCLK, so success was (in general) returned even
after an error was hit previously.

With this change, the function may now return success even if the final
preparation function fails, but it's probably enough to print a message
because (if successful) the real programming of the fuses has already
completed.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:41 +01:00
Tom Rini
1739564e75 Merge git://git.denx.de/u-boot-dm
Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:01:48 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Simon Glass
d11e8fd86e cros_ec: Fix uninitialised variable in cros_ec.c
This fixes this cppcheck report:

[drivers/misc/cros_ec.c:704]: (error) Uninitialized variable: req

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
2014-11-22 10:16:48 +01:00
Masahiro Yamada
4515992fc7 replace DIV_ROUND with DIV_ROUND_CLOSEST
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.

For example,
  foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
  foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Tom Rini
dee8abcd80 Merge git://git.denx.de/u-boot-x86 2014-10-23 06:54:03 -04:00