Commit graph

139 commits

Author SHA1 Message Date
Lokesh Vutla
a7638833b3 ARM: DRA7: Move emif settings to board specific files
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Lokesh Vutla
25afe55de5 ARM: DRA7: Enable EEPROM support
Enable EEPROM support for DRA74-evm.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Lokesh Vutla
e3ce3aa103 ARM: DRA7: emif: Check for enable bits before updating leveling output
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Kipisz, Steven
212f96f6bd board: ti: AM57xx: Add detection logic for AM57xx-evm
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).

The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.

Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.

NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.

This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:35 -04:00
Kipisz, Steven
74cc8b097d board: ti: beagle_x15: Rename to indicate support for TI am57xx evms
BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does
actually support two different platform configuration offered by
TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728
(or more commonly known as AM5728-evm).

Information about the TI AM57xx EVM can be found here
http://www.ti.com/tool/tmdxevm5728

The EVM configuration is 1-1 compatible with BeagleBoard X15 with the
additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push
button and TI's wlink8 offering.

Hence, we rename the beagle_x15 directory to am57xx to support TI
EVMs that use the AM57xx processor. By doing this we have common code
reuse. This sets the stage to have a common u-boot image solution for
multiple TI EVMs such as that already done for am335x and am437x. This
sets the stage for upcoming multiple TI EVMs that share the same code
base.

NOTE: Commit eae7ae1853 ("am437x: Add am57xx_evm_defconfig using
CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm
platform name. However, this ignored the potential confusion arising for
users as a result. To prevent this, existing beagle_x15_defconfig is
renamed as am57xx_evm_nodt_defconfig to denote that this is the "non
device tree" configuration for the same platform. We still retain
am57xx-beagle-x15.dts at this point, since we just require the common
minimum dts.

As a result of this change, users should expect changes in build
procedures('make am57xx_evm_nodt_defconfig' instead of 'make
beagle_x15_defconfig'). Hopefully, this would be a one-time change.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-11-18 08:47:03 -05:00
Paul Kocialkowski
9fd5401659 omap5: omap_die_id support
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:21 -04:00
Kishon Vijay Abraham I
504de98a3b ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()
Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:22 -04:00
Kishon Vijay Abraham I
ca5a0f172e ARM: OMAP5: Add functions to enable and disable USB clocks
Added functions to enable and disable USB clocks which can be invoked
during USB init and  USB exit respectively.

Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:21 -04:00
Kishon Vijay Abraham I
7beaf8b690 ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:19 -04:00
Nishanth Menon
76cff2b108 ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:13 -04:00
Nishanth Menon
c1ea3bece2 ARM: DRA7: Add detection of ES2.0
Add support for detection of ES2.0 version of DRA7 family of
processors. ES2.0 is an incremental revision with various fixes
including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp

[ravibabu@ti.com: posted internal for an older bootloader]
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:12 -04:00
Vignesh R
8a09cfe14b ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:14 +05:30
Tom Rini
0a9e34056f gpio: omap: Drop 'method' parameter
The "method" parameter was part of the original port of the driver from
the kernel.  At some point this may have been added to allow for future
differentiation (as omap1 and omap2 have different GPIO IP blocks, so
this wasn't an unreasonable thing to do).  At this point however it's
just extra overhead, so drop.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:48:06 -04:00
Nishanth Menon
095a5ef88e ARM: DRA72: disable workaround for 801819
DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.

Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-08-12 20:47:50 -04:00
Nishanth Menon
1bbb556a6a ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-08-12 20:47:50 -04:00
Paul Kocialkowski
d1a04b32f4 omap5: Definitions for SYS_BOOT-based fallback boot device selection
This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as
well as the memory-preferred scheme for the interpretation of each value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-07-27 15:02:09 -04:00
Nishanth Menon
67055bee25 ARM: DRA7: Change configuration to prevent DDR reset control from EMIF
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.

The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".

Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-19 16:46:48 -04:00
Tom Rini
7c352cd38d am33xx: Re-enable SW levelling for DDR2
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet.  In other cases
update the call to be as functional as before and check an already
programmed value in.

Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-15 10:57:26 -04:00
Lokesh Vutla
37be54fd13 ARM: BeagleBoard-x15: Enable i2c5 clocks
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:26 -04:00
Lokesh Vutla
71bed1855f ARM: DRA7: Add support for manual mode configuration
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.

struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
  And pass the offset of the CFG_XXX register in iodelay_cfg_entry.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
eda6fbcc8c ARM: DRA7: Add support for IO delay configuration
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.

IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
1f68451ca0 ARM: DRA7: Make do_set_mux32() generic
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
ee4dc2590f ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-12 12:43:07 -04:00
Lokesh Vutla
536d874708 ARM: DRA7: Update DDR IO registers
Update DDR IO register values.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:07 -04:00
Lokesh Vutla
a5c5c5b500 ARM: DRA7: Update DDR IO configuration
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
f308b4fce5 ARM: DRA72-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
920638fa5e ARM: DRA7-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling
on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
6213db78f4 ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Joe Hershberger
a26cd04920 arch: Make board selection choices optional
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2015-05-12 18:10:02 -04:00
Dileep Katta
f12467d1a5 ARM: DRA7: Set serial number environment variable
This patch populates serial number environment variable from
die_id_0 and die_id_1 register values for DRA7xx boards.

The function is added in omap common code so that this can be re-used.

Serial# environment variable will be useful to show correct
information in "fastboot devices" commands.

Ref:
http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-04-23 13:59:19 -04:00
Kishon Vijay Abraham I
4564faeafb ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.

Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-04-16 15:08:36 -04:00
Kishon Vijay Abraham I
d3cfcb3e2c ARM: DRA7: Enable clocks for USB OTGSS and USB PHY
Enabled clocks for dwc3 controller and USB PHY present in DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-14 05:48:08 +02:00
Nishanth Menon
fc7368ec85 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:13 -04:00
Praveen Rao
5f603761c3 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-13 09:29:01 -04:00
Lokesh Vutla
1860d10196 ARM: DRA7-evm: DDR3: Update leveling values
Update the software leveling parameters.
This fixes the random crash seen on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
Lokesh Vutla
802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
Angela Stegmaier
aa8ac43645 ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
Lubomir Popov
b558af8128 ARM: OMAP5: DRA7xx: Add support for power rail grouping
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.

This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.

The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.

Signed-off-by: Lubomir Popov <l-popov@ti.com>
2015-01-29 12:00:49 -05:00
Felipe Balbi
1e4ad74b87 beagle_x15: add board support for Beagle x15
BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60),
separate LCD port, video In port, 4GB eMMC, uSD,
Analog audio in/out, dual 1G Ethernet.

For more information, refer to:
http://www.elinux.org/Beagleboard:BeagleBoard-X15

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:39 -05:00
Felipe Balbi
eedd991611 arm: omap5: sdram: mark emif_get_ext_phy_ctrl_const_regs __weak
this will allow for boards to overwrite those
in case memory setup is different.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
29bc86ade9 arm: omap5: make hw_init_data weak
this way we can let boards overwrite based
on what they need.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
113d7e88cb arm: dra7xx: prcm: add missing registers
some boards might want to use USB1 for host,
without fiddling those registers it'll be
impossible.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Felipe Balbi
c27cd33b8c arm: omap5: tps659038: rename regulator defines
Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Georges Savoundararadj
2e07c249a6 kconfig: arm: introduce symbol for ARM CPUs
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.

For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.

Also, it removes redundant "string" type in some Kconfig files.

Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-29 09:02:09 -04:00
Masahiro Yamada
461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.

We can delete the ones in arch and board Kconfig files.

This commit can be easily reproduced by the following command:

find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
    N
    s/\n[[:space:]]*string//
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13 16:43:55 -04:00
R Sricharan
681f785f7c ARM: DRA72: DDR3: Add emif settings for 666MHz clock
On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-09-04 13:12:49 -04:00
Masahiro Yamada
6c5431ac81 omap5: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Sricharan R
f2a1b93b5c ARM: DRA7: Enable software leveling for dra7
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Lokesh Vutla
02847fcc92 ARM: DRA7xx: ctrl: Fix efuse register addresses
Efuse register addresses are wrongly programmed.
Fixing the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
Lokesh Vutla
9fcf3d3a1d ARM: DRA72x: Update EMIF data
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00