Use same dts to boot U-Boot and RISC-V
Linux Kernel v4.16-rc2 in ax25-ae350 platform.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Andes has rearranged the product combinations.
nx25 and ax25 both are RISC-V architecture cpu core.
But ax25 has MMU unit inside, and nx25 is not.
Cpu nx25 and platform ae250 are arranged in pairs.
Cpu ax25 and platform ae350 are arranged in pairs.
This patch will rename
nx25 as ax25
ae250 as ae350
nx25-ae250 as ax25-ae350
including filename, variable, string and definition.
Then u-boot can boot linux kernel in ae350
platform reasonably.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Fix license tags problem after apply patchs about
riscv: Enable efi_loader support.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
We have almost all pieces needed to support RISC-V UEFI binaries in place already.
The only missing piece are ELF relocations for runtime code and
data.
This patch adds respective support in the linker script and the runtime
relocation code. It also allows users to enable the EFI_LOADER configuration
switch on RISC-V platforms.
Signed-off-by: Alexander Graf <agraf@suse.de>
This patch adds an empty stub for board_quiesce_devices() which allows boards
to quiesce their devices before we boot into an OS in a platform agnostic way.
Signed-off-by: Alexander Graf <agraf@suse.de>
The hello world binary and a few selftests require to build EFI target
binaries, not just the EFI host environment.
This patch adds all required files to generate an EFI binary for
RISC-V.
Signed-off-by: Alexander Graf <agraf@suse.de>
The linker can remove sections that are never addressed, so it makes a lot
of sense to declare every function as an individual section.
This reduces the output U-Boot code size by ~30kb for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().
This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.
There are two methods to delivery dtb.
1 Pass from loader:
When u-boot boot from RAM, gdb or loader can pass dtb
via a2 to u-boot dynamically. Of course gdb or loader
shall be in charge of dtb delivery.
2 Configure CONFIG_SYS_FDT_BASE:
It can be configured as RAM or ROM base statically,
no mater u-boot boot from RAM or ROM.
If it was configured as ROM base, dtb can be burned
into ROM(spi flash) by spi driver.
Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
ATAGS is not supported and will be replaced
by DT in riscv-linux. So can be removed now.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
riscv-linux should use BBL (Berkeley bootloader) for
loading the Linux kernel.
U-Boot can play as FSBL(first stage bootloader)
to boot BBL and riscv-linux.
In BBL's init_first_hart(), it will pass dtb with a1.
So implement bootm to pass arguments to BBL correctly.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: static const char * array
should probably be static const char * const
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: Missing a blank line after declarations.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl.
CHECK: Alignment should match open parenthesis
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Add Kconfig and makefile for RISC-V
Also modify MAINTAINERS for it.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
Add header files for RISC-V.
Cache, ptregs, data type and other definitions are included.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
AE250 is the Soc using NX25 cpu core base on RISC-V arch.
Details please see the doc/README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.
Detail verification message please see doc/README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
