Commit graph

4 commits

Author SHA1 Message Date
Andrey Zhizhikin
50b1a69cee ARM: dts: imx8m: add UHS or HS400/HS400ES properties
i.MX8M series provide support for high speed grades in their
usdhc controllers, which has eMMC and SDHC connected to them.

Enable this support across the entire i.MX8M family by providing quirks
to usdhc controllers designated by storage media connected to them.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
2020-12-26 12:36:35 +01:00
Peng Fan
2634ba5743 arm: dts: imx8qm-mek: add u-boot, dm-spl for lpuart0
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL
is enabled. Since uclass power domain is also enabled, to make
lpuart work properly, need add u-boot,dm-spl for lpuart power domain
and its parent.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
84abc8d533 imx8qm: mek: enable dm-spl for pm
with u-boot,dm-spl added for imx8qm-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.

Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
0d331c035a imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT

Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2

U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)

CPU:   NXP i.MX8QM RevB A53 at 142933 MHz

Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot:  SD1
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:
Error: ethernet@5b040000 address not set.
eth-1: ethernet@5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00