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3 commits

Author SHA1 Message Date
Ye Li
dc77d0f9fc imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock 
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
 2022-02-05 13:38:39 +01:00
Ye Li
5ff18da34f imx8ulp: clock: Support LPAV clocks in cgc and pcc 
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
 2022-02-05 13:38:38 +01:00
Peng Fan
a84dab4f70 arm: imx8ulp: add clock support 
Add i.MX8ULP clock support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
 2021-08-09 14:46:51 +02:00