Sometimes, inside NetLoop, eth_halt() is called before eth_init() has
been called. This is harmless except for free() calls to pointers
which have not been allocated yet.
This patch initializes those pointers to NULL and allocates them only
the first time. This way we can get rid of free calls in halt callback.
This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes erroneous access to the ethernet PHY which broke the driver.
1. Selector field in the auto-negotiation register must be 0x00001 for
using 802.3, not 0x00000 which is reseved.
2. Access to the PHY address specified by CONFIG_FEC_MXC_PHYADDR, not
0x0 fixed address.
This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
Now using proper defines for auto-negotiation register.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
All currently available 4xx derivats have the I2C bootstrap EEPROM
located on I2C bus number 0. This patch now first sets this bus number,
so that the chip_config command also works for board with multiple
I2C busses, like Katmai.
Signed-off-by: Stefan Roese <sr@denx.de>
Both lpd7a400 and lpd7a404 failed to compile because they had
CONFIG_SMC_USE_IOFUNCS defined:
examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw'
Also removed an orphaned paren in lpd7a404.h
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes the following warnings:
Configuring for xaeniax board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - in operand of &
smc91111_eeprom.c:281: warning: suggest parentheses around + or - in operand of &
...
Configuring for xsengine board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - inside shift
smc91111_eeprom.c:281: warning: suggest parentheses around + or - inside shift
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The following error was seen on impa7 board, due to its use of a 32-bit bus
on CS8900.
cs8900.c:137:37: error: macro "get_reg_init_bus" passed 2 arguments, but takes just 1
This patch gives the macro the correct number of arguments
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The dev->halt() func can be called at any time, and the dev->recv() func
does not need to use NetRxPackets[] when calling NetReceive().
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Ensure all CS8900 data structures are assigned before accessing device
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes a problem only seen very occasionally on Canyonlands.
The NOR flash interface (CFI driver) doesn't work reliably in all cases.
Erasing and/or programming sometimes doesn't work. Sometimes with
an error message, like "flash not erased" when trying to program an
area that should have just been erased. And sometimes without any error
messages. As mentioned above, this problem was only seen rarely and with
some PLL configuration (CPU speed, EBC speed).
Now I spotted this problem a few times, when running my Canyonlands with
the following setup (chip_config):
1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
Changing the EBC configuration to not release the bus into high
impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
in EBC0_CFG) seems to fix this problem. I haven't seen any failure
anymore with this patch applied.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: David Mitchell <dmitchell@amcc.com>
Cc: Jeff Mann <MannJ@embeddedplanet.com>
Somehow I missed the NAND booting targets in the 4xx linker script
consolidation patchset. This patch fixes this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch introduces a weak default function for is_pci_host(),
returning 1. This is the default behaviour, since most boards only
implement PCI host functionality. This weak default can be overridden
by a board specific version if needed.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch consolidates the PPC4xx board specific PCIe configuration
code. This way the duplicated code is removed. Boards can implement a
special, non standard behaviour (e.g. number of PCIe slots, etc) by
overriding the weak default functions.
Signed-off-by: Stefan Roese <sr@denx.de>
The asm-arm/unaligned.h includes linux/unaligned/access_ok.h
This file is unsafe to be used on ARM, since it does an unaligned memory
accesses which fails on ARM.
Lookin at Linux the basic difference seems to be the header
"include/asm-arm/unaligned.h". The Linux version of "unaligned.h"
does *not* include "access_ok.h" at all. It includes "le_byteshift.h"
and "be_byteshift.h" instead.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Stefan Roese <sr@denx.de>
--
include/asm-arm/unaligned.h | 3 -
include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++
include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++
3 files changed, 142 insertions(+), 1 deletion(-)
create mode 100644 include/linux/unaligned/be_byteshift.h
create mode 100644 include/linux/unaligned/le_byteshift.h
The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should
not be including the immap_83xx.h when building 85xx. We can just get
this all from common.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The same code exists both inside an #ifdef and outside of it.
Remove the extra code for all the 86xx boards.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct. The function must return the first free
bus number for the next controller.
fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This reverts commit 70ed869ea5.
There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status. We can determine that
internally to fsl_pci_init_port. Revert the patch that makes the API
change.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
All these linker scripts can be removed since the new common ppc4xx
linker script should be able to handle all of those boards.
Please test and report problems. Thanks.
Signed-off-by: Stefan Roese <sr@denx.de>
This linker script can be used by all PPC4xx platforms. It works for
PPC405 and PPC440 platforms. Boards which need a board specific linker
script can override this default linker script in board/*/config.mk.
Signed-off-by: Stefan Roese <sr@denx.de>
These boards have special linker scripts right now. We can't use the
common 4xx linker script here. So overrride the linker script (LDSCRIPT)
in board/*/config.mk and choose the board specific version.
Signed-off-by: Stefan Roese <sr@denx.de>
Some 4xx Makefiles didn't add $(SOBJ) to their board library. This was
no till now problem, since those boards included this object (init.o
most of the time) directly from their linker scripts. This patch clean
this up, so that all objects are now collected in the board library. This
is in preparation for the upcoming PPC4xx linker script consolidation.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch extends the mkconfig script to automatically create a define
for the board directory in include/config.h:
#define CONFIG_BOARDDIR board/amcc/canyonlands
This is needed for the upcoming PPC4xx linker script consolidation,
where the PPC440 platforms need to include a board specific file in
the common linker script.
Signed-off-by: Stefan Roese <sr@denx.de>
We need loop-check the flash clear lock and enable bit for L2 cache.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds support for the board IPEK01 based on the MPC5200.
The Futjitsu Lime graphics controller is configured in 16 bpp mode.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words
for D32 accesses due to the diffferent connecting to the GDC bus. This
patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP,
which should be set for all board using the mb862xx in 16 bpp mode. For
the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
The new IPEK01 board can use the 32 bpp mode for the Lime graphics
controller. For this mode, video accelaration does not work. This patch
makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL,
which is enabled for the lwmon5 and the socrates board for backward
compatibility.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
The current transfer code relies on ctrlc() to abort transfers, but this
requires user interactivity. Naturalize the process with a timeout.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Proper behavior is to pull MAC address from NVRAM in the initialization() an
stuff it in dev->address, then program the device from dev->address in
the init() function.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The comment for the BR0_PRELIM port size initialization incorrectly
stated 32 bit, while it's actually 16 bit. The code is correct.
Reported-by: Guenter Koellner <guenter.koellner@nsn.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use
reset to retry. Define default bootcommand and bootargs for production.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
