Commit graph

3 commits

Author SHA1 Message Date
Praneeth Bajjuri
9c789fec10 arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 4266MTs DDR configuration.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2021-01-12 10:21:41 +05:30
Lokesh Vutla
196d3e4017 arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2020-01-03 09:47:10 -05:00
Lokesh Vutla
ec2fa9f76e arm: dts: k3-j721e: Add ddr node
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2019-10-25 17:33:21 -04:00