Commit graph

21080 commits

Author SHA1 Message Date
Jagannadha Sutradharudu Teki
29fbfc10f4 sf: Add debug messages on spi_flash_read_common
- Added debug's on spi_flash_read_common()
- Added space

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:10:36 +05:30
Jagannadha Sutradharudu Teki
95e779e4f4 sf: Place the sf calls in proper order
Placed the sf calls in proper order - erase/write/read

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:10:36 +05:30
Jagannadha Sutradharudu Teki
acc237544a sf: Unify spi_flash write code
Move common flash write code into spi_flash_write_common().

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:10:35 +05:30
Jagannadha Sutradharudu Teki
615a156167 sf: Add flag status register polling support
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.

Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
ba549de6c5 sf: Remove spi_flash_cmd_poll_bit()
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
76e98d4817 sf: spansion: Add support for S25FL512S_64K
Add support for Spansion S25FL512S_64K SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
4e2904311d sf: stmicro: Add support for N25Q1024A
Add support for Numonyx N25Q1024A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
221cb084ad sf: stmicro: Add support for N25Q1024
Add support for Numonyx N25Q1024 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
fd60c0ac31 sf: stmicro: Add support for N25Q512A
Add support for Numonyx N25Q512A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
0569f3b9be sf: stmicro: Add support for N25Q512
Add support for Numonyx N25Q512 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
f76b1bd08b sf: Use spi_flash_addr() in write call
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
1dcd6d0381 sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
fc207ee4db sf: Update sf read to support all sizes of flashes
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.

The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)

With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
e3ff9d51ec sf: Update sf to support all sizes of flashes
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility

The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.

As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
e612ddf593 sf: Read flash bank addr register at probe time
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.

bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.

Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
cf6b11dcda sf: Discover the bank addr commands
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.

Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:49 +05:30
Jagannadha Sutradharudu Teki
c9fcb59d7d sf: Add bank address register writing support
This patch provides support to program a flash bank address
register.

extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.

reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:49 +05:30
Axel Lin
9675fed474 spi: mxc_spi: Use DIV_ROUND_UP at appropriate places
This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-22 23:08:01 +05:30
Axel Lin
0cb8394f81 spi: cf_qspi: Use DIV_ROUND_UP at appropriate place
This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-22 23:08:01 +05:30
Jagannadha Sutradharudu Teki
1e77deec6e sf: winbond: Add support for W25QXXXFV
Add support for Winbond W25QXXXFV SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22 23:08:01 +05:30
Jagannadha Sutradharudu Teki
f0293fb595 sf: winbond: Add support for W25Q16DW
Add support for Winbond W25Q16DW SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22 23:08:01 +05:30
Jagannadha Sutradharudu Teki
920559f19e sf: winbond: Add support for W25Q128FW
Add support for Winbond W25Q128FW SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22 23:08:00 +05:30
Jagannadha Sutradharudu Teki
e9fd312088 sf: winbond: Update the names for W25Q 0x40XX ID's flash parts
Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22 23:08:00 +05:30
Jagannadha Sutradharudu Teki
6fd1000224 sf: spansion: Correct name of S25FL128S 64K Sector part
Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156a)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22 23:08:00 +05:30
Mike Dunn
9dc8fef258 pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled.  Tested
on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
84c617beb2 pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune.  This will cause
gcc to define the __XSCALE__ macro.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
097d86d098 pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off.  Tested on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
3497d43215 pxa: palmtreo680 flash programming utility
This adds a userspace linux utility that writes the u-boot image to an mtd
partition on the docg4 nand flash.

A special utility is required to do this because u-boot is partially loaded by
an initial program loader (IPL) that is permanently programmed to the boot
region of the flash.  This IPL expects the image to be written in a unique
format. The characteristics of this format can be summarized as follows:
  - Flash blocks to be loaded must have a magic number in the oob bytes of the
    first page of the block.
  - Each page must be written redundantly in the subsequent page.
  - The integrated flash controller's "reliable mode" is used, requiring that
    alternate 2k regions (4 pages) are skipped when writing.
For these reasons, a u-boot image can not be written using nandwrite from
mtd-utils.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
0dc0e846f3 pxa: add support for palmtreo680 board
This patch adds support for the Palm Treo 680 smartphone.  A quick overview of
u-boot implementation on the treo 680...

The treo 680 has a Diskonchip G4 nand flash chip.  This device has a 2k region
that maps to the system bus at the reset vector in a NOR-like fashion so that it
can be used as the boot device.  The phone is shipped with this 2k region
configured as write-protected (can't be modified) and programmed with an initial
program loader (IPL).  At power-up, this IPL loads the contents of two flash
blocks to SDRAM and jumps to it.  The capacity of the two blocks is not large
enough to hold all of u-boot, so a u-boot SPL is used.  To conserve flash space,
these two blocks and the necessary number of subsequent blocks are programmed
with a concatenated spl + u-boot image.  That way, the IPL will also load a
portion of u-boot proper, and when the spl runs, it relocates the portion of
u-boot that the IPL has already loaded, and then resumes loading the remaining
part of u-boot before jumping to it.

The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think
that having a writable environment was worth the cost of a flash block, although
adding it would be straightforward.  I abuse the CONFIG_EXTRA_ENV_SETTINGS
option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV).

Support for the LCD is included, but currently it is only useful for displaying
the u-boot splash screen.  But if u-boot is built without the usbtty console, it
does display the auto-boot progress nicely.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Albert ARIBAUD
fbf87b1823 arm: optimize relocate_code routine
Use section symbols directly
Drop support for R_ARM_ABS32 record types
Eliminate unneeded intermediate registers
Optimize relocation table iteration

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:50 +02:00
Albert ARIBAUD
47bd65ef05 arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.

__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:29 +02:00
Albert ARIBAUD
d026dec875 arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.

Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:05 +02:00
Albert ARIBAUD
df84502edf arm: generalize lib/bss.c into lib/sections.c
File arch/arm/lib/bss.c was initially defined for BSS only,
but is now going to also contain definitions for other
section-boundary-related symbols, so rename it for better
accuracy.

Also, remove useless 'used' attributes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:43 +02:00
Albert ARIBAUD
09d81184e1 remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase

Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:05 +02:00
Albert ARIBAUD
c37980c31a arm: ensure u-boot only uses relative relocations
Add a Makefile target ('checkarmreloc') which
fails if the ELF binary contains relocation records
of types other than R_ARM_RELATIVE.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 22:59:20 +02:00
Scott Wood
9b80aa8ec9 nand: Don't call adjust_size_for_badblocks for erase
adjust_size_for_badblocks reduces the operation size to account
for the block skipping done by the read/write functions when an
interval (partition name or whole chip) is specified rather than a data
amount.

Erase does not do block skipping, except for erase.spread which takes
a data amount rather than an interval (and thus already does not call
adjust_size_for_badblocks).  Calling adjust_size_for_badblocks when
block skipping is not done means that if bad blocks are present,
the "nand erase.part" and "nand erase.chip" commands will fail to erase
blocks at the end of the interval.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Harvey Chapman <hchapman@3gfp.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-06-21 11:47:43 -05:00
Ajay Kumar
9169543d1e video: exynos_fb: Add the missing #else clause
This patch fixes a bug introduced while adding DT support
to Exynos FIMD driver:

	commit c23f3157d6
	Author: Ajay Kumar <ajaykumar.rs@samsung.com>
	Date:   Thu Feb 21 23:53:01 2013 +0000

	    video: exynos_fb: add DT support for FIMD driver

Even though this part of code was missing, things were working
fine on Exynos5250 because, samsung_get_base_fimd() used
to give the correct base address for Exynos5250 FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-21 09:14:15 +09:00
Simon Glass
b2f794125e exynos: Enable mmc for snow
Snow has an internal eMMC and an external SD card. Enable these in the
device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-21 09:08:46 +09:00
Chunhe Lan
5707233880 powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
Prabhakar Kushwaha
bd7c023e48 powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
init_tlbs() initialize all the TLB entries required for the system.

So disable DEBUG TLB entry before TLB entries initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
York Sun
5bdeff3214 powerpc/pixis: Fix pixis help message
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:52 -05:00
Chris Packham
0d3efd8056 powerpc/CoreNet: Allow pbl images to take u-boot images != 512K
Instead of assuming that SYS_TEXT_BASE is 0xFFF80000 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also increase the size of the memory buffer to
accommodate a larger output image.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:52 -05:00
Axel Lin
e51e47d38e powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:51 -05:00
Ying Zhang
f90572d91b Makefile: move the common makefile line to public area
Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.

This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:51 -05:00
Ying Zhang
ba1bee43ec common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL
There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:51 -05:00
Ying Zhang
67ad0d52df powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Ying Zhang
5df572f013 powerpc/mpc85xx: support application without resetvec segment in the linker script
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Prabhakar Kushwaha
505c293ffd board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define
PCIe TLB should be created with CONFIG_PCI defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Prabhakar Kushwaha
4d0e6e0d73 board/b4860qds: Relax NOR flash teadc timing parameter
Relax parameters to give address latching more time to setup.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00