TPL is introduced in the patch "NAND: TPL : introduce the TPL
based on the SPL", here enable TPL for p1022ds nand boot.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.
Conflicts:
arch/arm/include/asm/arch-am33xx/hardware.h
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
[trini: Change to SPDX, fix a few compiler warnings, adapt to
CONFIG_OMAP_COMMON]
Signed-off-by: Tom Rini <trini@ti.com>
Update omap5_common.h to use ti_armv7_common.h, and in turn update
dra7xx_evm.h and omap5_uevm.h slightly. The biggest changes here are
that IP blocks which exist on the platform, and had clocks enabled,
now have the drivers being built as well.
Signed-off-by: Tom Rini <trini@ti.com>
We create two new files, include/configs/ti_armv7_common.h for all of
the common IP blocks and related features / commands we share in
virtually all of our platforms. We then create
include/configs/ti_am335x_common.h for everything common to the am335x
SoC leaving just the board specific parts to
include/configs/ti_am335x_common.h.
Signed-off-by: Tom Rini <trini@ti.com>
We defined PHYS_DRAM_1 to 0x80000000 (start of DRAM) and then used this
for CONFIG_SYS_SDRAM_BASE. But then we kept on referencing PHYS_DRAM_1
in other places. Change to directly setting CONFIG_SYS_DRAM_BASE and
then using that name in code.
Signed-off-by: Tom Rini <trini@ti.com>
IGEP boards now have Device Tree support in the mainline
kernel. To boot an IGEP board using a DT, a uEnv.txt plain
text file could be used to define a custom uenvcmd that will
be run by the default boot command.
It is more convenient to change the default boot command to
allow loading a FDT if it is stored in the boot dir of the
rootfs uSD/MMC partition.
If no FDT is found then the defaul command tries to boot a
zImage without a DT using legacy boot.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Able to load the kernel from some form of ext[234] or FAT. Also, with v3.9 and
later of the Linux Kernel, uImage isn't builtable anymore by default, so we
should switch to use the bootz command.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
As config was originally based on am335x_evm.h we have also some
duplicate / unnused #defines.
Commit 15191c91 removed these #defines on various AM335x boards but not
for IGEP COM AQUILA. This patch simply removes them for this board.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Add to the default environment the possibily to boot from NAND using
a ubi rootfs. Also the partition scheme is set as follows:
Start Size
SPL : 0x00000000 0x00080000 (512KiB)
U-Boot : 0x00080000 0x00100000 (1MiB)
U-Boot Env : 0x00180000 0x00020000 (128KiB)
File System : 0x001C0000 -
The ubiboot script gets the kernel and the dtb file from the boot directory
of the File System.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Now, the default kernel to boot the IGEP COM AQUILA is device tree based. As
old kernel is deprecated we should adapt the boot commands to use DTB files.
Also, with v3.9 and later of the Linux Kernel, uImage isn't builtable anymore
by default, so we should switch to use the bootz command.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
After commit:
79cd2f814b config_cmd_default.h: Remove CONFIG_CMD_MEMTEST
It's not necessary to undef the CONFIG_CMD_MEMTEST, so we can remove it from
configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Adding a new CONFIG_OMAP_COMMON which is included by all boards
that needs to build cpu/armv7/omap-common folder.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fix the license header introduced by the following patches
Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board
Signed-off-by: York Sun <yorksun@freescale.com>
This patch changes some features of the a3m071/a4m2k board support:
- Add bootcounter support
- Update MTD env default to correct values
- Add mtdparts to bootargs for mtd partitioning via kernel cmdline
- Added some default env variables for easy updating (kernel, dtb)
- Change README to the updated flash locations
Signed-off-by: Stefan Roese <sr@denx.de>
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module. It
includes C293PCIE board, C293PCIE board and C291PCIE board.
- 512KB platform SRAM in addition to 512K L2 Cache/SRAM
- 512MB soldered DDR3 32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
[yorksun: Fixup include/configs/C29XPCIE.h]
Signed-off-by: York Sun <yorksun@freescale.com>
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
1) Add support in B4860 board files for using IDT driver where
IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
that generate different refclks for SerDes modules, used this driver
for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
for CPRI to work. CPRI works on 122.88MHz and default refclks coming
on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
to b4860qds board file, as SerDes1 Refclk1 would come from
PHY MUX in case of certain protocols, that have been checked here.
This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB.
DDR changed from DDR2 1G to DDR3 2G.
NAND: 128 MiB
Flash: 64 MiB
Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
ECC for DDR is disabled due the procedure to load images
No board FPGA (QIXIS)
NOR flash has 32-bit port for higher loading speed
IFC and I2C timing don't really matter, so set them fast
No ethernet
Signed-off-by: York Sun <yorksun@freescale.com>
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: York Sun <yorksun@freescale.com>
TWR-P1025 Specification:
-----------------------
Memory subsystem:
512MB DDR3 (on board DDR)
64Mbyte 16bit NOR flash
One microSD Card slot
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC3: Connected to Atheros AR8035 GETH PHY
UART:
Two UARTs are routed to the FDTI dual USB to RS232 convertor
USB: Two USB2.0 Type A ports
I2C:
AT24C01B 1K Board EEPROM (8 bit address)
QUICC Engine:
Connected to DP83849i PHY supply two 10/100M ethernet ports
QE UART for RS485 or RS232
PCIE:
One mini-PCIE slot
Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
In case only the CONFIG_SYS_I2C_SPEED is set in configuration file,
the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED.
The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver.
Unfortunatelly, due to a typo in the driver, instead of defining
CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined
and therefore the driver failed to compile. The same applies for
CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well.
This patch fixes the issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Aside from microblaze, all other SoCs/boards/vendors store their DT files
in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this
location for consistency.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Some boards, such as the BeagleBone Black, have an eMMC chip intstead
of NAND. We can use the eMMC boot partition to store the environment,
since it isn't used for anything else. This allows us to have a
configurable environment on those boards.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
The BeagleBone Black can boot from either the MMC card
or eMMC chip on board. We should try both interfaces.
This modification also allows a graceful fallback if
a device exists but boot images are not present on it.
Changes for v2:
* Fix boot partition - it should always show up as mmcblk0p2
* Fix missing FDT load
Signed-off-by: Justin Waters <justin.waters@timesys.com>
