Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.
Signed-off-by: Simon Glass <sjg@chromium.org>
This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.
This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than each device having its own way to allocate a SPI flash
structure, use the new allocation function everywhere. This will make it
easier to extend the interface without breaking devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is difficult to extend the SPI flash structure since
all devices allocate it themselves, and few of them zero all fields.
Add a new function spi_flash_alloc() which can be used by SPI devices
to perform this allocation, and thus ensure that all devices can
better cope with SPI structure changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than each driver having its own way to allocate a SPI slave,
use the new allocation function everywhere. This will make it easier
to extend the interface without breaking drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is difficult to extend the SPI structure since all
drivers allocate it themselves, and few of them zero all fields. Add
a new function spi_alloc_slave() which can be used by SPI drivers
to perform this allocation, and thus ensure that all drivers can
better cope with SPI structure changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end. We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.
Conflicts:
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot.lds
arch/arm/lib/Makefile
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/dvlhost/u-boot.lds
board/freescale/mx31ads/u-boot.lds
doc/README.scrapyard
include/configs/tegra-common.h
Build tested for all of ARM and run-time tested on am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
Use the ability to have several active EHCI controller on a system
in the PCI EHCI controller implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
[port of Linux kernel commit bcd218be5aeb by Steve Glendinning]
The eeprom read & write commands currently check the E2P_CMD_LOADED_ bit is
set before allowing any operations. This prevents any reading or writing
unless a correctly programmed EEPROM is installed.
Signed-off-by: Michael Spang <spang@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
The interrupt endpoint handling code stores the buffer pointer in the QH
padding field. We need to make it the size of a pointer to avoid strict
aliasing issue with the compiler.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Interrupt transfers aren't meant to be used from the async list
(the EHCI spec indicates trouble with low/full-speed intr on async).
Build a periodic list instead, and provide an API to make use of it.
Then, use that API from the existing interrupt transfer API.
This provides support for USB keyboards using EHCI.
Use timeouts to ensure we cannot get stuck in the keyboard scanning
if something wrong happens (USB device unplugged or fatal I/O error)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Enabling the non-dt path for the driver so that
we don't get any build errors for non-dt configuration.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
With current FDT support driver tries to parse device node
twice in ehci_hcd_init() and ehci_hcd_stop(), which shouldn't
happen ideally.
Making provision to store data in a global structure and thereby
passing its pointer when needed.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
This patch adds the USB Mass Storage Gadget to u-boot
New command called "ums" is implemented to provide access
to on-device embedded persistent memory.
USB Mass Storage is supposed to work on top of the USB
Gadget framework
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Marek Vasut <marek.vasut@gmail.com>
The storage_common.c source file from v2.6.36 Linux kernel.
commit d26a6aa08b9f12b44fb1ee65625e7480d3d5bb81
Author: Michal Nazarewicz <m.nazarewicz@samsung.com>
Date: Mon Nov 9 14:15:23 2009 +0100
USB: g_mass_storage: code cleaned up and comments updated
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Marek Vasut <marek.vasut@gmail.com>
This commit fixes problems with some non-standard requests send with
device address instead of interface address (bmRequestType.Receipent field).
This happens with dfu-util (debian version: 0.5), which address non standard
requests (like w_value=0x21 and bRequest=GET_DESCRIPTOR) to device.
Without this fix, the above request is STALLED, and hence causes dfu-util
to assume some standard configuration (packet size = 1024B instead of 4096B)
In turn it displays following errors:
Error obtaining DFU functional descriptor
Warning: Assuming DFU version 1.0
Warning: Transfer size can not be detected
...
Warning: Trying default transfer size 1024
This fix allows passing non-standard request to function setup code, where
it shall be handled.
Tested at: Trats (exynos4210)
Tested with:DFU and UMS gadgets
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
When both CONFIG_USB_GADGET & CONFIG_USB_ETHER are defined
the makefile links objects twice.
This patch uses a Makefile specific idiom of
'if defined(CONFIG_USB_GADGET) || defined(CONFIG_USB_ETHER)'
to handle the case.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Dealing with raw block numbers with the dfu is very annoying.
Introduce a partition method.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Zero out timeout value; letting it filled with undefined values
ends up with the dfu host hanging.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
On EHCI controller with 64-bit address space support, we must initialize
properly the high word for the PCI bus master accesses.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Instead of hardcoding the PCI IDs on the USB controller, use the PCI
class to detect them.
Ensure the busmaster bit is properly set in the PCI configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
This cast does not seem correct, since we should be writing to a pointer,
not a ulong.
This fixes the following warning on nds32:
-ns16550.c:49: warning: passing argument 2 of 'writeb' makes pointer from integer without a cast
Signed-off-by: Simon Glass <sjg@chromium.org>
Tegra30 requires the SD Bus Voltage & Power bits be set in the SD
Power Control register. Tegra20 works w/o them set, but do it anyway
for those SoCs as it's part of the SD spec. Also call a common
board pad init routine (pad_init_mmc) in mmc_reset(), used by
Tegra30 only for now.
Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a
new compatible entry is used in the fdt compat_names/id tables.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.
Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.
Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
The ehci_hcd entry points were just calling into the Tegra USB
functions. Now that they are in the same file we can just move over the
implementation.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This moves the Tegra USB implementation into the drivers/usb/host
directory. Note that this merges the old
/arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code
changes, just moving stuff around.
v2: While at it also move some defines and the usb.h header file to make
usb driver usable for Tegra30.
NOTE: A lot more work is required to properly init the PHYs and PLL_U on
Tegra30, this is just to make porting easier and it does no harm here.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch corrects the following issues
1) Write the correct M/T Stop value to I2CSTAT after i2c write.
According to the spec, after finish the data transmission, we should
write a M/T Stop (I2C_MODE_MT | I2C_TXRX_ENA) to I2CSTAT instead of
a M/R Stop (I2C_MODE_MR | I2C_TXRX_ENA).
2) Not split the write to I2CSTAT into 2 steps in i2c read.
According to the spec, we should write the combined M/R Start value to
I2CSTAT after setting the slave address to I2CDS
3) Fix the mistake of making an equality check to an assignment.
In the case of I2C write with the zero-length address, while tranfering the
data, it should be an equality check (==) instead of an assignment (=).
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This revomes the code under #if 0 in the s3c24x0_i2c driver.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch changes sdhci_init()'s behavior to NOT enable all interrupt
sources by default. Moreover interrupt signaling has been disabled.
This patch do not enable interrupts which aren't served in u-boot
(they are defined at sdhci.h but NOT used elsewhere):
- SDHCI_INT_CARD_INSERT, SDHCI_INT_CARD_REMOVE, SDHCI_BUS_POWER,
SDHCI_INT_CARD_REMOVE, SDHCI_INT_CARD_INT
Special care shall be put on SDHCI_INT_CARD_INT, which indicates
interrupt generated by SD card.
According to "SD Host Controller Simplified Spec. ver 3.00" when bit 8
(Card Interrupt Status Enable) at "Normal Interrupt Status Enable
Register" (offset 0x34) is set, the card interrupt detection is started.
Then eMMC card may cause the SD controller to set this bit and then this
interrupt is passed to booted OS and might cause kernel crash.
To sum up:
- Only enable interrupts, which are served at u-boot
- This cleanup as a side effect fixes SDHCI's CARD INTERRUPT problem at
Linux kernel (versions 3.6+, sdhci controller)
- Keep masked bits at "Normal Interrupt Signal Enable Register" (0x38h)
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adding Exynos Thermal Management Unit driver to monitor SOC
temperature and take actions corresponding to states of TMU.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
These boards seem to be unmaintained for quite some time. So lets
remove support for them completely. This also cleans up some
common drivers/files.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Guillaume Alexandre <guillaume.alexandre@gespac.ch>
Acked-by: Wolfgang Denk <wd@denx.de>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation
doesn't work. This patch fixes this function changing the read loop and reading the
onenand blocks from page to page.
Tested with various IGEP based boards with a OneNAND from Numonyx.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded
in the code. This forces anyone who wants to use a different gfx_format to make
adjustments after calling omap3_dss_panel_config(). This could be avoided if the
value of gfx_format were parameterized as input for omap3_dss_panel_config().
Make gfx_format a field in struct panel_config, and update existing structs to
set this field to the value that was originally hard coded.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Currently there's no appropriate place to store driver specific data
because the pointer that is meant for that (priv) is being used to
store the base address of mmc registers.
Introduce a new struct for storing driver specific data.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
There are 3 MMC/SD/SDIO controllers in OMAP SoCs, but only 2 structs
are defined for devices. This leads to data being written outside of
array bounds on systems that use all 3 controllers.
Update hsmmc_dev array to the correct size.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
This patchs adds support for MAX98095 codec in
sound driver.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds the driver for codec MAX98095 required by Snow
Board
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rework ehci-mxs so it supports both ports on MX28. It was necessary
to wrap the per-port configuration into struct ehci_mxs_port and pull
out the clock configuration function.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The ehci-mxs driver included the register definitions directly.
Use imx-regs.h instead since it contains proper handling of the
differences between mx23 and mx28.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
The CONFIG_MXS_SPI_DMA_ENABLE is no longer relevant as the SPI DMA
has proven to work correctly. Remove this configuration option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The MX23 has slightly different register layout. Adjust the SPI
driver to match the layout, both the PIO and DMA part.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.
First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.
Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.
Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.
Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Including header for pads is not needed and breaks board
after renaming pin definitions.
Series-to: u-boot
Series-cc: marex@denx.de,fabio.estevam@freescale.com,eric.nelson@boundarydevices.com
Signed-off-by: Stefano Babic <sbabic@denx.de>
Spi driver for bf60x is different from old one, so implement a new
driver for it.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Add rsi/sdh support for bf60x.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Implements the tstc() interface for the serial driver. Multiplexing
the console between the serial port and a keyboard uses a polling
method of checking if characters are available; this means that the
serial console must be non-blocking when attempting to read
characters.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit 8b710b1 started removing code for the unmaintained "ns9750dev"
board; the board support is still broken, and not included anywhere in
the Makefile or boards.cfg. Remove the remaining dead code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
If the NAND is locked tight, commands such as lock and unlock will not
work, but the NAND chip may not report an error. Check the lock tight
status before attempting such operations so that an error status can be
reported if we know the operation will not succeed.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The differences include the number of GPIOs and that one is
not required to set the pinmux on request.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of
kernel version 3.7.5. If the driver is used for the da850, then SoC
variant must be specified by CONFIG_SOC_DA850.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
Cc: Tom Rini <trini@ti.com>
If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code
instead of the 1-bit error correction code on the NAND device
within this driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for configuring tegra SPI driver from devicetree.
Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts
file for spi controller to describe seaboard spi.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for Numonyx N25Q256A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q32A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q32 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q64A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Winbond's W25Q64W SPI flash.
This device is used on xilinx zynq emulation platform.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch corrected the first byte of idcode1 for S25FL256S SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_ARM_DCC_MULTI should be also removed in the patch
"serial: Remove CONFIG_SERIAL_MULTI from serial drivers"
(sha1: a382725060)
Because the driver defines serial_* functions
which cause conflict with serial.c (multiple definition of serial_*)
Removing CONFIG_SERIAL_MULTI function also require to define
default_serial_console for cases where another serial driver
is not available in the system.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
Currently we have "unsigned long blkcnt" which is fine with
CONFIG_SYS_64BIT_LBA undefined because "lbaint_t" is basically the same
"unsigned long".
If CONFIG_SYS_64BIT_LBA gets defined "lbaint_t" is defined as "unsigned
long long".
Even though not many embedded systems have CONFIG_SYS_64BIT_LBA defined
it's good to have types in function implementation that match exactly
with prototypes.
Signed-off-by: Alexey Brodkin <alexey.brodkin@gmail.com>
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
System ACE compact flash controller supports either 8-bit (default) or
16-bit data transfers. And in corresponding driver we need to implement
read/write of 16-bit data words properly for both modes of operation.
In existing code if width==8 both branches get executed which may cause
unexpected behavior of SystemAce controller.
Addition of "else" fixes described issue and execution is done as
expected for both (8-bit and 16-bit) data bus widths.
Signed-off-by: Alexey Brodkin <alexey.brodkin@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The local functions in the mxs i2c driver are not marked static, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
The MX23 has different layout of DMA channels. Fix the MMC
driver to support MX23.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This does the same reset mask as done in v3.7 Linux kernel code.
The block is properly configured for MMC operation that way.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
It is useful to be able to try a range of
possible phy addresses to connect.
Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Only the hardware ethernet registers are needed
for this function, so don't pass the more general
structure. I'm trying to separate MII and fec.
This also fixes MX28 fec_mii_setspeed use on secondary ethernet port
This was found by inspection of the code and should be
checked on real hardware.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
It is more logical to test for CONFIG_FEC_MXC_PHYADDR
to determine whether to define the function fecmxc_initialize.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
The MX23 can only use two SSP ports.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The clock data are not used by the driver, drop them.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Instead of storing the computed line length in a local variable, store
it in the global lcd_line_length variable to make sure the LCD subsystem
can properly draw content for the display resolution.
This probably wasn't noticed yet because the only board where LCD
support is currently enabled is Seaboard, which runs at a 1366x768
resolution. As it happens this is the maximum resolution supported and
also the default that is used to initialize the framebuffer before the
configuration from DT is available.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Previously, the call to draw_logo() was happening irrespective
of whether we have selected logo or LCD console.
With this patch we call draw_logo() only when CONFIG_CMD_BMP is selected.
This would even fix the following compilation warning:
exynos_fb.c: In function 'draw_logo':
exynos_fb.c:74:8: warning: variable 'addr' set but not used
[-Wunused-but-set-variable]
exynos_fb.c:73:9: warning: variable 'y' set but not used
[-Wunused-but-set-variable]
exynos_fb.c:73:6: warning: variable 'x' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove unused variable disp_info to fix the following compilation warning:
exynos_dp.c: In function 'exynos_init_dp':
exynos_dp.c:860:23: warning: variable 'disp_info' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch resolves the following build errors for I2C driver in
VCMA9:
In file included from s3c24x0_i2c.c:40:0:
s3c24x0_i2c.h:38:17: error: field 'id' has incomplete type
s3c24x0_i2c.c:70:39: error: 'CONFIG_MAX_I2C_NUM' undeclared here (not
in a function) s3c24x0_i2c.c:70:31: warning: 'i2c_bus' defined but
not used [-Wunused-variable] s3c24x0_i2c.c:72:12: warning:
'i2c_busses' defined but not used [-Wunused-variable]
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that
does not set the TEMT bit when the transmitter is empty in SPL.
This makes U-Boot to hang while waiting for TEMT to be set.
Add a new option to avoid this:
CONFIG_SYS_NS16550_BROKEN_TEMT
16550 UART set the Transmitter Empty (TEMT) Bit when all output
has finished and the transmitter is totally empty. U-Boot waits
for this bit to be set to initialize the serial console. On some
broken platforms this bit is not set in SPL making U-Boot to
hang while waiting for TEMT. Define this option to avoid it.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.
This patch enables this PPB protection mechanism for all AMD type
(AMD commandset) chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection status is ignored.
This patch now reads the current sector protection status and uses
it for these AMD/Spansion flash chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Consolidate manufacturer matching into the function manufact_match()
and use it.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).
For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.
Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Signed-off-by: Stefan Rose <sr@denx.de>
Currently, exynos FIMD driver is being used to support only TIZEN LOGOs.
In order to get LCD console, we need to enable half word swap feature
of FIMD and use 16 BPP.
LCD console and proprietary Logo cannot be used simultaneously.
We use "logo_on" field inside vidinfo_t structure to decide whether
user wants Logo or Console.
Define CONFIG_CMD_BMP and make logo_on = 1 to get Logo on screen.
Use logo_on = 0 to get output console on LCD.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
lcd_set_flush_dcache(1) function is called from exynos_fb.c configuration file
to enable lcd_sync function.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Adding fdt support to ehci-exynos in order to parse
register base addresses from the device node.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds FDT support to the SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds FDT support to the codec.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds FDT support to the sound driver.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Functions added to get the I2C bus number and reset I2C bus using
FDT node.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
All esdhc variants we know should support high capacity MMC cards,
so let's add MMC_MODE_HC host_caps unconditionally to support those
MMC cards (capacity > 2 GB).
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
Well, not terminating the list causes very interesting crashes.
As in changing the vendor & product ID crashes. Fun.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Andy Fleming <afleming@freescale.com>
CC: Zang Roy-R61911 <tie-fei.zang@freescale.com>
CC: Kumar Gala <galak@kernel.crashing.org>
In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
It could happen (1 out of 100 times) that NAND did not start up correctly after
warm rebooting, so we end up with various failures or DMA timed out due to a
stalled BCH. When resetting BCH together with GPMI, the issue could not be
observed anymore (after 10000+ reboots). We probably need the consistent state
already before sending commands to NAND. This behaviour was observed in barebox
and kernel, so I assume it affects U-Boot as well. I chose to keep the extra
reset for BCH when changing the flash layout to be on the safe side.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.
This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This patch modifies the S3C i2c driver to support both Exynos4 and Exynos5
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
OMAP5 has 8b i2c data register field, like OMAP2, 3 and 4. Handle in the same
way. This fixes the following error on OMAP5:
OMAP5430 EVM # mmc rescan
timed out in wait_for_bb: I2C_STAT=1410
twl6035: could not turn on LDO9.
Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.
The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
The I2C block reset configures the I2C bus speed to strange value.
Read the I2C speed from the block before reseting the block and
restore it afterwards, so the I2C operates correctly. This issue
can be replicated by doing unsuccessful I2C transfer, after such
transfer finishes, the I2C block clock speed is misconfigured.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
According to FSL, the value in the TIMING2 register shall be 0x00300030
instead of what's written in the datasheet. This new value correlates
with older STMP36xx datasheet. Issues were detected in Linux when this
register was misconfigured, so write this correct value.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Use i2c_set_bus_speed() in i2c_init() within the mxs i2c driver
to avoid duplication of code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This patch implements the setup and retrieval functions for the I2C
bus speed on the MXS I2C IP.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This patch pulls out the I2C speed setup from the i2c_init() call
and implements the bus configuration lookup table with register
values that needs to be programmed into the I2C IP to run at
particular speed.
This patch is a first step towards implementing run-time I2C bus
speed configuration for the MXS I2C IP.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Some functions in the MXC i2c driver were not static, fix this by
making them so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Moved the pmic_max77686.c max77686_pmic.h to drivers/power
and made required changes accordingly
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We handle i2c_write return code and complain in case of error. We propagate the
error, too, to allow better handling at the upper level in the future.
Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
We add a return code to wait_for_bb() to be able to report errors to the
callers properly. We in turn handle this new error code in i2c_read, i2c_write
and i2c_probe.
Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
Added posted writes (read after writes) to effect the
change immediately for channel confiuration and channel
enable register
Disable the channel to purge receieve data in TX_ONLY
mode transfer otherwise rx data will get affected by
the next immediate RX_ONLY mode transfer
Wait for the EOT bit to be set after last byte has been
loaded to TX shift register in the the TX_ONLY mode.This
ensures TX data has been completely shifted out
Disable the channel in RX_ONLY mode before reading the
last data from RXX register to prevent the SPI slave
to transmit next word
Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in>
Cc: Tom Rini <trini@ti.com>
Cc: jacopo mondi <j.mondi@voltaelectronics.com>
AM33XX with BCH8 can't work with nand_spl_simple correctly
because custom read_page implementation is required for proper
syndrome generation.
This simple driver mostly duplicates nand_spl_simple but has
nand_read_page changed to suit our needs.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
The at91sam9m10g45 also support WDRBT bit, add support for it
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Conflicts:
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/woodburn_common.h
board/woodburn/woodburn.c
These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.
Fix all conflicts and update woodburn to use Power Framework.
Signed-off-by: Stefano Babic <sbabic@denx.de>
If the pl011 is connected to another device which has hardware
flow-control on, characters are never received by the pl011.
Asserting RTS when flow-control is off will have no effect.
This is in line with how Linux behaves.
Signed-off-by: Joshua Housh <joshua.housh@calxeda.com>
Tested-by: Marek Vasut <marex@denx.de>
This command will start erasing at memory address zero
if there is not a valid framebuffer address that was found
during video_init().
This is a common case with Chrome OS devices in normal mode
when we do not execute the video option rom in coreboot.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.
BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
them all, or even keep track of the new ones.
So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not
connected. When serial cable is not connected, serial error occurs and
some garbage comes in data register.
sh_serial_tstc() in serial_sh.c does not check error status and misunderstand
there is some input data. It is the reason that autoboot fails.
This patch adds checking error status in sh_serial_tstc().
This patch is based on v2013.01-rc1 tag of u-boot master git.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.
Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.
Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.
Update the MXS MMC driver for this change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Bring in the code from Linux kernel.
Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <dilinger@queued.net>
Date: Fri Jul 4 10:00:03 2008 -0700
Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.
Signed-off-by: Rommel G Custodio <sessyargc@gmail.com>
CC: Andy Fleming <afleming@freescale.com>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <afleming@freescale.com>
The interpretation of the data returned by the MMC_CMD_ALL_SEND_CID
command was incorrect with respect to the JEDEC Standard No. 84-A441.
This change makes the interpretation correct with respect to the
defined fields of the CID register.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND Flash is erased by blocks, not by pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
This patch cleans up nand_util.c:
- Fix tabs.
- Fix typos.
- Remove space character before opening parenthesis in function calls.
- Fix comments.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[scottwood@freescale.com: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: updated for makefile changes earlier in patchset
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
It's arch code and not a driver, so move it where it belongs. When it
originally went into drivers/misc there was no 8xxx CPU directory.
This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
TEMT is set when the transmitter is totally empty and all output has
finished.
This prevents output problems (including a loss of synchronization
observed on p2020 that persisted for quite a while) if SPL has output
still on its way out.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: fixed typo in subject, and explained what the bit does in the changelog
CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic
ns16550 output code without pulling in things not needed by the SPL.
This previously only worked with non-MULTI configs. Recently MULTI was
made mandatory, and MIN_FUNCTIONS fails like this:
drivers/serial/libserial.o: In function `calc_divisor.clone.0':
serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to `get_bus_freq'
drivers/serial/libserial.o: In function `_serial_getc':
(.text._serial_getc+0x30): undefined reference to `NS16550_getc'
drivers/serial/libserial.o: In function `_serial_tstc':
(.text._serial_tstc+0x30): undefined reference to `NS16550_tstc'
drivers/serial/libserial.o: In function `_serial_setbrg':
(.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit'
make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1
make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2
With MIN_FUNCTIONS we don't need anything from this file, so don't build
it. The conditional needs to be in the file itself rather than the
makefile, because the config symbols are only imported to the makefiles
once, not separately for the SPL phase of the build.
Signed-off-by: Scott Wood <scottwood@freescale.com>
By commit c7e3b2b5, this was chanded to support multiple controllers.
But this has missing of parenthesis. This commit fix it.
-----
r8a66597-hcd.c: In function ‘usb_lowlevel_init’:
r8a66597-hcd.c:911:52: error: expected declaration specifiers before ‘)’
token
r8a66597-hcd.c:935:1: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or‘__attribute__’ before ‘{’ token
r8a66597-hcd.c:939:1: error: expected ‘{’ at end of input
-----
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Lucas Stach <dev@lynxeye.de>
Some variables are initialized with a value defined by macro.
This was changed to use the macro directly. And the variable not to
use deleted it.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Backend driver for MUSB OTG controllers found on TI AM35x.
It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with non-updated core registers.
This confuses the code and result in hanged transfers.
Add a small delay in am35x_interrupt as a workaround.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Existing U-Boot musb driver has no support for the new gadget framework
and also seems to have other limitations. As gadget framework is ported
from Linux it seems pretty natural to port musb gadget driver as well.
This driver supports both host and peripheral modes.
This is not a replacement for current musb driver (at least now) as
there are still some consumers of the old UDC interface.
No DMA operation support included, CONFIG_MUSB_PIO_ONLY should be
defined.
Virtual root hub device is not implemented.
Known problems: with no devices connected usb_lowlevel_start() fails.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.
As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.
Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.
This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
If a board has all 8 data lines routed, the SD/MMC controller can still
operate in 4-bit (or presumably even 1-bit) mode. Adjust Tegra's MMC
driver to report the 4-bit capability even for 8-bit slots.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for CONSOLE_MUX to tegra-kbc driver. This requires
adding a flag to struct keyb to know the driver has already been
initialized so if we try to initialize it again we can just return
success. Also call into iomux_doenv() from drv_keyboard_init to
re-evaluate the stdin string.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for selecting the required cache mode for the LCD:
off, write-through or write-back.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This driver supports driving a single LCD and providing a U-Boot console
on it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance
selection bit.
This issue has been reported by Eric Bénard <eric@eukrea.com> and fixed by
Christoph Fritz <chf.fritz@googlemail.com> on Linux, from which these #define-s
had been copied.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance
selection bit.
This issue has been reported by Michael Burkey <mdburkey@gmail.com> and fixed by
Christoph Fritz <chf.fritz@googlemail.com> on Linux, from which these #define-s
had been copied.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.
Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
In decode_cs() function the polarity of the chip select must be taken into
account.
Also, for the case of low active chip select, the CS was activated too early.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
A custom board_ehci_hcd_init() may be unneeded, so add a weak default
implementation doing nothing.
By the way, use simple __weak from linux/compiler.h for
board_ehci_hcd_postinit() instead of weak alias with full attribute.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Make EHCI power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like
MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT,
not the opposite.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Clean up ehci-mxc:
- Remove useless #if's.
- Fix identation.
- Issue a #error if used with an unsupported platform.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This patch adds SPI driver for EXYNOS.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds driver for audio codec WM8994
Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds driver for I2S interface specific to samsung.
Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch fixes image position on screen when images's height or width is biger then the lcd's.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch is fixing the following errors
s3c64xx.c:175: error: variable 's3c64xx_serial_drv' has initializer but incomplete type
s3c64xx.c:176: error: unknown field 'name' specified in initializer
s3c64xx.c:176: warning: excess elements in struct initializer
s3c64xx.c:176: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:177: error: unknown field 'start' specified in initializer
s3c64xx.c:177: warning: excess elements in struct initializer
s3c64xx.c:177: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:178: error: unknown field 'stop' specified in initializer
s3c64xx.c:178: warning: excess elements in struct initializer
s3c64xx.c:178: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:179: error: unknown field 'setbrg' specified in initializer
s3c64xx.c:179: warning: excess elements in struct initializer
s3c64xx.c:179: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:180: error: unknown field 'putc' specified in initializer
s3c64xx.c:180: warning: excess elements in struct initializer
s3c64xx.c:180: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:181: error: unknown field 'puts' specified in initializer
s3c64xx.c:181: warning: excess elements in struct initializer
s3c64xx.c:181: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:182: error: unknown field 'getc' specified in initializer
s3c64xx.c:182: warning: excess elements in struct initializer
s3c64xx.c:182: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c:183: error: unknown field 'tstc' specified in initializer
s3c64xx.c:183: warning: excess elements in struct initializer
s3c64xx.c:183: warning: (near initialization for 's3c64xx_serial_drv')
s3c64xx.c: In function 's3c64xx_serial_initialize':
s3c64xx.c:188: warning: implicit declaration of function 'serial_register'
s3c64xx.c: At top level:
s3c64xx.c:191: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'struct'
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Now proper GPIO parts numbering is handled at Samsung devices.
This fix is necessary for code using GPIO located at other banks
than first.
Test HW:
- Exynos4210 - Trats
- S5PC110 - goni
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
if a board uses the vcxk driver option CONFIG_SYS_VCXK_DOUBLEBUFFERD,
compilier shows warnings. This patch will fix it.
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Two extra commands:
"pmic name bat state" and "pmic name bat charge" has been added to
pmic framework. Those provides state display and charge capabilities
to named batteries.
The pmic_core.c file has been refactored to more consistent name scheme.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Function for calculating LDO internal register value from passed micro
Volt.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Support for MAX17042 fuel-gauge (FG), which is built into the MAX8997
power management device.
Special file - fg_battery_cell_params.h with cells characteristics
added.
The FG device will work with redesigned PMIC framework.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Support for MUIC (Micro USB Integrated Circuit) built into the MAX8997
power management device.
The MUIC device will work with redesigned PMIC framework.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Trats battery is now treated in the same way as other power related
devices. This approach allows for more unified handling of all devices
responsible for power management.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
The PMIC framework has been moved to its more natural place
./drivers/power from ./drivers/misc directory.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The PMIC framework has been extended to support multiple instances of
the variety of devices responsible for power management.
This change allows supporting of e.g. fuel gauge, charger, MUIC (Micro USB
Interface Circuit).
Power related includes have been moved to ./include/power directory.
This is a first of a series of patches - in the future "pmic" will be
replaced with "power".
Two important issues:
1. The PMIC needs to be initialized just after malloc is configured
2. It uses list to hold information about available PMIC devices
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
PMIC MAX8997 is now ready to work with single and multibus soft I2C
implementation.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Since the pmic_reg_read is the u32 value, the order in which bytes
are placed to form u32 value is important.
Support for big and little sensor endianess is added.
Moreover calls to [leXX|beXX]_to_cpu have been added to support
little and big endian SoCs.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This patch adds support for proper handling of a PMIC I2C transmission
comprising of two bytes.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
implement the common api lcd_setcolreg in include/lcd.h
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[agust: fixed commit log and gcc 4.6 -Wparentheses warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Use CONFIG_MX6 when the particular processor
variant isn't important.
Reserve the use of CONFIG_MX6Q to
specifically test for quad cores variant.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
The cfb console driver is trying to prevent bitmaps to spill over the
screen, but the calculations assume that at least part of the bitmap
fits into the screen area. In reality there could be bitmap elements
which are completely out of the screen area, they just need to be
discarded.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement the new video API functions to provide access to screen size,
etc.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
The gadget ethernet driver needs to keep copies of the MAC address (at
both endpoints) as strings so it needs a custom function for validation
of the MAC. It was not however performing a totally correct check and
also was emitting a warning about a set but unused variable. The
solution to both is that after checking the string contents we use the
standard test for a valid MAC.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static?
nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static?
nand_base.c:2854:1: error: directive in argument list
nand_base.c:2856:1: error: directive in argument list
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
cfi_flash.c:756:43: warning: Using plain integer as NULL pointer
cfi_flash.c:1150:52: warning: cast to non-scalar
cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89)
cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f)
cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
fsl_esdhc.c:71:6: warning: symbol 'esdhc_xfertyp' was not declared. Should it be static?
fsl_esdhc.c:413:6: warning: symbol 'set_sysctl' was not declared. Should it be st
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mmc.c:137:5: warning: symbol 'mmc_send_cmd' was not declared. Should it be static?
mmc.c:203:5: warning: symbol 'mmc_send_status' was not declared. Should it be static?
mmc.c:247:5: warning: symbol 'mmc_set_blocklen' was not declared. Should it be static?
mmc.c:440:5: warning: symbol 'mmc_read_blocks' was not declared. Should it be static?
mmc.c:510:5: warning: symbol 'mmc_go_idle' was not declared. Should it be static?
mmc.c:532:1: warning: symbol 'sd_send_op_cond' was not declared. Should it be static?
mmc.c:597:5: warning: symbol 'mmc_send_op_cond' was not declared. Should it be static?
mmc.c:661:5: warning: symbol 'mmc_send_ext_csd' was not declared. Should it be static?
mmc.c:683:5: warning: symbol 'mmc_switch' was not declared. Should it be static?
mmc.c:705:5: warning: symbol 'mmc_change_freq' was not declared. Should it be static?
mmc.c:775:5: warning: symbol 'sd_switch' was not declared. Should it be static?
mmc.c:796:5: warning: symbol 'sd_change_freq' was not declared. Should it be static?
mmc.c:935:6: warning: symbol 'mmc_set_ios' was not declared. Should it be static?
mmc.c:953:6: warning: symbol 'mmc_set_bus_width' was not declared. Should it be static?
mmc.c:1108:26: warning: dubious: !x & y
mmc.c:960:5: warning: symbol 'mmc_startup' was not declared. Should it be static?
mmc.c:1243:5: warning: symbol 'mmc_send_if_cond' was not declared. Should it be s
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
input.c:97:5: warning: symbol 'input_queue_ascii' was not declared. Should it be
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
mpc83xx_gpio.c:166:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_f'
mpc83xx_gpio.c:190:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_r'
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
sata_sil.c:371:7: warning: symbol 'sil_sata_rw_lba28' was not declared. Should it be static?
sata_sil.c:399:7: warning: symbol 'sil_sata_rw_lba48' was not declared. Should it be static?
sata_sil.c:429:6: warning: symbol 'sil_sata_cmd_flush_cache' was not declared. Should it be static?
sata_sil.c:441:6: warning: symbol 'sil_sata_cmd_flush_cache_ext' was not declared. Should it be static?
sata_sil.c:489:7: warning: symbol 'sata_read' was not declared. Should it be static?
sata_sil.c:505:7: warning: symbol 'sata_write' was not declared. Should it be static?
sata_sil.c:526:5: warning: symbol 'init_sata' was not declared. Should it be static?
sata_sil.c:588:5: warning: symbol 'scan_sata' was not declared. Should it be static?
fsl_sata.c:59:6: warning: symbol 'dprint_buffer' was not declared. Should it be static?
fsl_sata.c:187:42: warning: incorrect type in assignment (different base types)
fsl_sata.c:187:42: expected unsigned int [unsigned] [usertype] cda
fsl_sata.c:187:42: got restricted __le32 [usertype] <noident>
fsl_sata.c:291:6: warning: symbol 'fsl_sata_hardware_reset' was not declared. Should it be static?
fsl_sata.c:418:27: warning: incorrect type in assignment (different base types)
fsl_sata.c:418:27: expected unsigned int [unsigned] [usertype] dba
fsl_sata.c:418:27: got restricted __le32 [usertype] <noident>
fsl_sata.c:424:41: warning: incorrect type in assignment (different base types)
fsl_sata.c:424:41: expected unsigned int [unsigned] [usertype] ext_c_ddc
fsl_sata.c:424:41: got restricted __le32 [usertype] <noident>
fsl_sata.c:431:41: warning: incorrect type in assignment (different base types)
fsl_sata.c:431:41: expected unsigned int [unsigned] [usertype] ext_c_ddc
fsl_sata.c:431:41: got restricted __le32 [usertype] <noident>
fsl_sata.c:442:22: warning: incorrect type in assignment (different base types)
fsl_sata.c:442:22: expected unsigned int [unsigned] [usertype] cda
fsl_sata.c:442:22: got restricted __le32 [usertype] <noident>
fsl_sata.c:446:31: warning: incorrect type in assignment (different base types)
fsl_sata.c:446:31: expected unsigned int [unsigned] [usertype] prde_fis_len
fsl_sata.c:446:31: got restricted __le32 [usertype] <noident>
fsl_sata.c:448:22: warning: incorrect type in assignment (different base types)
fsl_sata.c:448:22: expected unsigned int [unsigned] [usertype] ttl
fsl_sata.c:448:22: got restricted __le32 [usertype] <noident>
fsl_sata.c:460:28: warning: incorrect type in assignment (different base types)
fsl_sata.c:460:28: expected unsigned int [unsigned] [usertype] attribute
fsl_sata.c:460:28: got restricted __le32 [usertype] <noident>
fsl_sata.c:623:6: warning: symbol 'fsl_sata_flush_cache' was not declared. Should it be static?
fsl_sata.c:667:5: warning: symbol 'fsl_sata_rw_ncq_cmd' was not declared. Should it be static?
fsl_sata.c:710:6: warning: symbol 'fsl_sata_flush_cache_ext' was not declared. Should it be static?
fsl_sata.c:725:6: warning: symbol 'fsl_sata_software_reset' was not declared. Should it be static?
fsl_sata.c:760:5: warning: symbol 'ata_low_level_rw_lba48' was not declared. Should it be static?
fsl_sata.c:795:5: warning: symbol 'ata_low_level_rw_lba28' was not declared. Should it be static?
the following compiler warnings show up after fixing the above, so
remove those three functions:
fsl_sata.c:59:13: warning: 'dprint_buffer' defined but not used [-Wunused-function]
fsl_sata.c:291:13: warning: 'fsl_sata_hardware_reset' defined but not used [-Wunused-function]
fsl_sata.c:726:13: warning: 'fsl_sata_software_reset' defined but not used [-Wunused-function]
Other than that, the following are fixed by __iomem annotation:
fsl_sata.c:84:39: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:84:39: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:84:39: got unsigned int volatile *addr
fsl_sata.c:172:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:172:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:172:26: got unsigned int *<noident>
fsl_sata.c:175:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:175:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:175:19: got unsigned int *<noident>
fsl_sata.c:181:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:181:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:181:19: got unsigned int *<noident>
fsl_sata.c:184:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:184:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:184:26: got unsigned int *<noident>
fsl_sata.c:186:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:186:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:186:19: got unsigned int *<noident>
fsl_sata.c:189:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:189:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:189:26: got unsigned int *<noident>
fsl_sata.c:191:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:191:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:191:19: got unsigned int *<noident>
fsl_sata.c:194:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:194:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:194:26: got unsigned int *<noident>
fsl_sata.c:195:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:195:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:195:19: got unsigned int *<noident>
fsl_sata.c:198:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:198:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:198:19: got unsigned int *<noident>
fsl_sata.c:201:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:201:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:201:19: got unsigned int *<noident>
fsl_sata.c:204:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:204:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:204:26: got unsigned int *<noident>
fsl_sata.c:205:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:205:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:205:19: got unsigned int *<noident>
fsl_sata.c:208:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:208:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:208:26: got unsigned int *<noident>
fsl_sata.c:209:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:209:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:209:19: got unsigned int *<noident>
fsl_sata.c:212:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:212:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:212:26: got unsigned int *<noident>
fsl_sata.c:213:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:213:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:213:19: got unsigned int *<noident>
fsl_sata.c:216:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:216:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:216:19: got unsigned int *<noident>
fsl_sata.c:219:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:219:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:219:19: got unsigned int *<noident>
fsl_sata.c:222:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:222:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:222:19: got unsigned int *<noident>
fsl_sata.c:225:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:225:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:225:26: got unsigned int *<noident>
fsl_sata.c:227:19: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:227:19: expected unsigned int volatile [noderef] <asn:2>*addr
fsl_sata.c:227:19: got unsigned int *<noident>
fsl_sata.c:242:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:242:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:242:26: got unsigned int *<noident>
fsl_sata.c:256:32: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:256:32: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:256:32: got unsigned int *<noident>
fsl_sata.c:262:26: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:262:26: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:262:26: got unsigned int *<noident>
fsl_sata.c:274:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:274:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:274:53: got unsigned int *<noident>
fsl_sata.c:275:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:275:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:275:53: got unsigned int *<noident>
fsl_sata.c:276:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:276:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:276:53: got unsigned int *<noident>
fsl_sata.c:277:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:277:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:277:53: got unsigned int *<noident>
fsl_sata.c:278:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:278:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:278:53: got unsigned int *<noident>
fsl_sata.c:279:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:279:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:279:53: got unsigned int *<noident>
fsl_sata.c:280:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:280:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:280:53: got unsigned int *<noident>
fsl_sata.c:281:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:281:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:281:53: got unsigned int *<noident>
fsl_sata.c:282:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:282:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:282:53: got unsigned int *<noident>
fsl_sata.c:283:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:283:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:283:53: got unsigned int *<noident>
fsl_sata.c:284:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:284:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:284:53: got unsigned int *<noident>
fsl_sata.c:285:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:285:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:285:53: got unsigned int *<noident>
fsl_sata.c:286:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:286:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:286:53: got unsigned int *<noident>
fsl_sata.c:287:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:287:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:287:53: got unsigned int *<noident>
fsl_sata.c:288:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:288:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:288:53: got unsigned int *<noident>
fsl_sata.c:289:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:289:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:289:53: got unsigned int *<noident>
fsl_sata.c:290:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:290:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:290:53: got unsigned int *<noident>
fsl_sata.c:291:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:291:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:291:53: got unsigned int *<noident>
fsl_sata.c:292:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:292:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:292:53: got unsigned int *<noident>
fsl_sata.c:293:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:293:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:293:53: got unsigned int *<noident>
fsl_sata.c:294:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:294:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:294:53: got unsigned int *<noident>
fsl_sata.c:295:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:295:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:295:53: got unsigned int *<noident>
fsl_sata.c:296:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:296:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:296:53: got unsigned int *<noident>
fsl_sata.c:297:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:297:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:297:53: got unsigned int *<noident>
fsl_sata.c:298:53: warning: incorrect type in argument 1 (different address spaces)
fsl_sata.c:298:53: expected unsigned int const volatile [noderef] <asn:2>*addr
fsl_sata.c:298:53: got unsigned int *<noident>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?
Note: in the ping.c fix, commit a36b12f95a
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
Currently, this driver uses a 28bit interface to AHCI, this
limits the number of blocks addressable to 2^28, or the max
disk size to 512(2^28) or about 137GB. This change allows
supporting drives up to about 2TB.
Testing this is a bit difficult. There is test code that
can be inserted into U-Boot that will write test patterns
into certain unused blocks. These patterns can be manually
checked using 'dd' after boot. Another way is to confirm the
original error that exposed this bug is fixed. IOW: see if
AU (Auto Update) will now work on the drive. Also, check
that there are no warning messages from the 'cgpt' utility.
Signed-off-by: Walter Murphy <wmurphy@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Writes in u-boot are so rare, and the logic to know when is
the last write and do a flush only there is sufficiently
difficult. Just do a flush after every write. This incurs,
usually, one extra flush when the rare writes do happen.
Signed-off-by: Marc Jones <marc.jones@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add HDD handling to the SSD-only AHCI driver, by separately dealing with
spin-up and link-up.
Signed-off-by: Marc Jones <marc.jones@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Note: These are timeout values and not delay values, so the event being
timed out will complete whenever it is actually ready, with a
measurement granularity of 1 millisecond, up till the timeout value.
Therefore, there is no effect on SSD booting.
The values were determined by instrumenting the code and measuring the
actual time taken by several different models of HDD for each of the
parameters and then adding 50% more for the spinup value and just
doubling the command timeout value.
Signed-off-by: Walter Murphy <wmurphy@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Exynos5 automatically performs DMA when the SATA controller executes
commands. This adds the necessary dcache-to-memory flush &
invalidation calls to allow the DMA to properly function.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the assignment of various physical memory buffers used by the
SATA controller to explicitly be denoted as physical addresses.
The memory is identity-mapped, so these function calls are a nop, but
they provide good semantic documentation for any maintainers.
The return value of virt_to_phys() is 'unsigned long'. On machines
where sizeof(unsigned long) != sizeof(pointer), a cast through
(uintptr_t) is needed to appease the compiler due to the potential of
losing the upper 32 bits of the address.
In compilation this scenario, a physical address could be 64-bits, yet
the C pointer environment only allows 32-bit addresses; the constraint
is that pointers cannot address more than 4Gb of memory and if
virt_to_phys() ever returns an out-of-range value for the physical
address, there are issues with emmory mapping which must be solved.
However, since the memory is identify mappeed, there is no problem
introducing the cast: the original pointer will reside in 32-bits, so
the physical address will also be within in 32-bits.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This fixes a spelling error in a message which can be output to the
console.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This cleanup replaces the hardcoded use of '20', which represents the
number of bytes in the FIS, with sizeof(fis).
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs,
the small value is the only value with the correct size. If it supports more,
if the number of sectors is small enough to fit into 28 bits, both fields
reflect the correct value. If it's too large, the smaller field has 28 bits of
1s, 0xfffffff, and the other field has the correct value.
The AHCI driver is implemented by attaching to the generic SCSI code and
translating on the fly between SCSI binary data structures and AHCI data
structures. It responds to requests to execute specific SCSI commands by
executing the equivalent AHCI commands and then crafting a response which
matches what a SCSI disk would send.
The AHCI driver now considers both fields and chooses the correct one when
implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The "scsi write" command requires support from underlying driver.
This CL enables SCSI_WRITE10 in AHCI driver.
Tested in U-Boot console, try to i/o with sector #64:
scsi read 1000 40 1
md.b 1000 200 # check if things are not 0xcc
mw.b 1000 cc 200 # try to fill with 0xcc
scsi write 1000 40 1
mw.b 1000 0 200 # fill with zero
md.b 1000 200 # should be all 0
scsi read 1000 40 1
md.b 1000 200 # should be all 0xcc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This command doesn't really do anything when talking to a SATA device, and
sending it confuses some of them. This change makes sending the command
optional, and defaults to not. The situations where it should be sent are not
the common case.
With the standard SSD in the machine, here are some times with the option
turned off:
1. 8277
2. 8273
3. 8050
And turned on:
1. 8303
2. 8155
3. 8276
Sending that command seems to have no meaningful effect on performance.
This fixes problems with an SSD marked Toshiba NV6424, Taiwan 11159AE P
and TC58NVG5D2FTA10.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
- print the correct speed
- print all the AHCI capability flags
(information taken from Linux kernel driver)
- clean up some comments
For example, this might show the following string:
AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
- remove unused ssleep macro
- add some useful debugging information
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The existing code waits a whole second for the AHCI controller to reset.
Instead, let's poll the status register to see if the reset has
succeeded and return earlier if possible. This brings down the time for
AHCI probing from 1s to 20ms.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
With an Intel AHCI controller, the driver does not operate properly
if the requested amount of blocks to read exceeds 255.
It is probably possible to specify 0 as the block count and the driver
will read 256 blocks, but it was decided to limit the number of blocks
read at once to 128 (it should be a power of 2 for the optimal
performance of solid state drives).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Add optional support for some ANSI escape sequences to the
cfb_console driver. Define CONFIG_CFB_CONSOLE_ANSI to enable
cursor moving, color reverting and clearing the cfb console
via ANSI escape codes.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.
This is also already done on other FPGA's, e.g. Stratix.
Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add the missing bits to the Tegra NAND driver to make ONFI detection work
properly.
Also add it to the Tegra default config, as it seems to be a reasonable thing
to have it available on all boards that use any kind of NAND.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Introduce FSL_PMIC_I2C_LENGTH to configure the number of bytes that are used to
communicate with the PMIC via I2C.
Instead of hardcoding the value, pass the number via a configurable option per
PMIC type.
This will be useful for adding support for PMIC MC34704 from Freescale, which
uses only one byte in its I2C protocol.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
serial_ns16550.c:222:1: warning: symbol 'eserial1_init' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_setbrg' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_getc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_tstc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_putc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_puts' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_init' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_setbrg' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_getc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_tstc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_putc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_puts' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_init' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_setbrg' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_getc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_tstc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_putc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_puts' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_init' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_setbrg' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_getc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_tstc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_putc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_puts' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
fsl_i2c.c:217:14: warning: symbol 'get_i2c_clock' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.
At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The endpoint rx count register value will be zero if it is read before
receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.
Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before
reading endpoint rx count register. Proceed with rx count read and
FIFO read only if RXPKTRDY bit is set.
Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.
So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.
struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT
not defined.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is EP or RC mode.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This driver is no longer used and it's remaining users were converted
to the new generic PXA MMC driver. Thus, remove this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
MMC host controller requires a delay between every sdhci_send_cmd()
execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay
of 1000us was provided after every mmc_send_cmd() call. Adding a quirk
in current sdhci driver to replicate the behaviour.
Without this delay, MMC initialization on Origen board fails with
following error messages.
Timeout for status update!
mmc fail to send stop cmd
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In host-control register, DMA select bit field is present.
BUt in sdhci.c, didn't select for DMA.
if set CONFIG_MMC_SDMA, we need to set SDMA-select bit.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timeout value is tunable.
When run read/write operation, sometime returned the timeout error.
Because the timeout value is too short.
So increased the enough timeout value.
(This timeout value is used to prevent the infinite loop.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The recent removal of the cmd->flags field caused error in the
debuging code of mmc_spi. Fix this:
mmc_spi.c: In function 'mmc_spi_request':
mmc_spi.c:179:2: error: 'struct mmc_cmd' has no member named 'flags'
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Implement necessary code to use the generic bounce buffer routines
inside this driver. This replaces the MMC bounce buffer, which is
to be removed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
when missing USB PHY clock, u-boot will hang during USB
initialization when issuing "usb start". We should check
USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case.
Due to controller issue of PHY_CLK_VALID in ULPI mode, we set
USB_EN before checking PHY_CLK_VALID, otherwise PHY_CLK_VALID
doesn't work.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to
translate key code into escape sequence.
(Updated by sjg@chromium.org to move away from a function to store
keycodes, so we can easily record how many were sent. We now need to
return this from input_send_keycodes() so we know whether keys were
generated.)
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
The i8042 keyboard reset was not checking the results of the output
buffer after the reset command. This can jam up some KBC/keyboards.
Also, remove a write to the wrong register and the CONFIG setting
around the incorrect write.
Signed-off-by: Marc Jones <marc.jones@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
The BIOS leaves the keyboard enabled during boot time so that any
keystroke would interfere kernel driver initialization.
Add a way to disable the keyboard to make sure no scancode will be
generated during the boot time. Note that the keyboard will be
re-enabled again after the kernel driver is up.
This code can be called from the board functions.
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
This change adds a board overridable function which can be used to decide
whether or not to initialize the i8042 keyboard controller. On systems where
it isn't actually connected to anything, this can save a significant amount of
boot time.
On Stumpy, this saves about 200ms on boot.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
On x86, the i8042 keyboard controller driver frequently waits for the keyboard
input buffer to be empty to make sure the controller has had a chance to
process the data it was given. The way the delay loop was structured, if the
controller hadn't cleared the corresponding status bit immediately, it would
wait 1ms before checking again. If the keyboard responded quickly but not
instantly, the driver would still wait a full 1ms when perhaps 1us would have
been sufficient. Because udelay is a busy wait anyway, this change decreases
the delay between checks to 1us.
Also, this change gets rid of a hardcoded 250ms delay.
On Stumpy, this saves 100-150ms during boot.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
