Commit graph

87 commits

Author SHA1 Message Date
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Siva Durga Prasad Paladugu
dd12a27ce2 net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Siva Durga Prasad Paladugu
f0b94c4bcd net: zynq_gem: Dont flush dummy descriptors
Dont flush dummy descriptors as they are already
allocated from a region with dcache off. Tested
this on Zynq(zc702) and ZynqMP(zcu102) boards.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Siva Durga Prasad Paladugu
dea004e41a net: zynq_gem: Use wait_for_bit with non breakable
Use wait_for_bit to be non breakable as using it with
breakable causes issue of un interruptible auto negotiation.
This is due to the ctrlc pressed will taken for wait_for_bit()
abort during phy_read() and hence not coming out of
auto negotiation.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02 14:44:20 -05:00
Olliver Schinagl
b233089787 net: zynq_gem: Do not return -ENOSYS on success
The .read_rom_hwaddr net_ops hook does not check the return value, which
is why it was never caught that we are currently returning 0 if the
read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.

In this case we can simplify this by just returning the result of the
function.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-06-02 14:44:18 -05:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Tom Rini
b504ff9f6b Xilinx changes for v2017.05
- Move to DM clk driver
 - Add clk support for zynq_sdhci
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Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.05

- Move to DM clk driver
- Add clk support for zynq_sdhci
2017-03-16 16:44:23 -04:00
Nathan Rossi
2c2ab8d65f net: zynq_gem: Fix masking of supported phydev features
When the zynq_gem driver initializes the phy it sets the supported
features that the phy can support and advertise. However instead of
masking the supported features such that it limits the available
features it sets the phy to have the exact supported features of the
zynq_gem. This is problematic as it will enable features that a phy does
not have or cannot advertise.

Specifically this appears as an issue when using a phy that is only
capable of 10/100, but the zynq_gem driver will override this and try to
enable and advertise 10/100/1000.

Reported-by: Arno Steffens <star@gmx.li>
Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN")
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Tested-by: Arno Steffens <star@gmx.li>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-03-07 11:27:33 -06:00
Stefan Herbrechtsmeier
781745bd87 zynq: Move zynq to clock framework
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
eff55c55c7 net: zynq: Add clk framework support to zynq ethernet driver
If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
a259243e9d net: zynq: Don't overwrite gem_rclk_ctrl with default value
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Siva Durga Prasad Paladugu
a765bdd1cb net: zynq_gem: Use clock driver for ZynqMP
Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:12 +01:00
Michal Simek
b908fcad84 net: gem: Use wait_for_bit() instead of private mdio_wait()
Using generic wait_for_bit() implementation instead of
using private wait function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:11 +01:00
Michal Simek
6516e3f253 net: xilinx: Use mdio_register_seq() to support multiple instances
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.

Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-20 07:40:04 +01:00
Tom Rini
361a879902 Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"
This reverts commit 3edc0c2522, reversing
changes made to bb135a0180.
2016-12-09 07:56:54 -05:00
Michal Simek
b63cb3abbc net: xilinx: Use mdio_register_seq() to support multiple instances
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.

Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
2016-12-08 10:34:42 +01:00
Michal Simek
15a2acdf85 common: miiphyutil: Work and report phy address in hex in mdio cmd
It is confusing that mdio commands work and report phy id as
decimal value when mii is working with hex values.

For example:
ZynqMP> mdio list
gem:
21 - TI DP83867 <--> ethernet@ff0e0000
ZynqMP> mdio read ethernet@ff0e0000 0
Reading from bus gem
PHY at address 21:
0 - 0x1140
ZynqMP> mii dump 21 0
Incorrect PHY address. Range should be 0-31
...
ZynqMP> mii dump 15
0.     (1140)                 -- PHY control register --
  (8000:0000) 0.15    =     0    reset

U-Boot normally takes hex values that's why this patch is changing mdio
command to handle hex instead of changing mii command to handle decimal
values.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-02 14:36:02 +01:00
Siva Durga Prasad Paladugu
4eaf8f5424 net: zynq_gem: Correct SGMII enable bit setting
Correct the SGMII enable bit position to 27 instead
of 31.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-15 15:28:01 +01:00
Siva Durga Prasad Paladugu
27183d7c22 net: zynq_gem: Modify the nwcfg bit definitions
Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-15 15:28:00 +01:00
Masahiro Yamada
5d97dff042 treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>
Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>.
Replace all include directives for <asm-generic/errno.h> with
<linux/errno.h>.

<asm-generic/...> is supposed to be included from <asm/...> when
arch-headers fall back into generic implementation. Generally, they
should not be directly included from .c files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add drivers/usb/host/xhci-rockchip.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 22:25:27 -04:00
Tom Rini
2ee490a024 Merge branch 'master' of git://git.denx.de/u-boot-net
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/zynq_gem.c
2016-05-24 11:59:02 -04:00
Dan Murphy
20671a9896 net: zynq_gem: Add the passing of the phy-handle node
Add the ability to pass the phy-handle node offset
to the phy driver.  This allows the phy driver
to access the DT subnode's data and parse accordingly.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Michal Simek
7a673f0b06 phy: Wire return value from phy_config()
Fix zynq_gem driver to handle error from phy_config correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:17:59 +02:00
Michal Simek
55259e7cda net: xilinx: Handle error value from phy_startup()
Handle error returned by phy_startup() properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:55 +02:00
Siva Durga Prasad Paladugu
845ee5f623 net: zynq_gem: Add SGMII support for zynqMP
PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:39 +02:00
Siva Durga Prasad Paladugu
e76d2dcaeb net: zynq_gem: Return error incase of invalid phy address
Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:39 +02:00
Joe Hershberger
a509a1d402 net: gem: Allow to set the MAC from an EEPROM
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.

Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:27:54 +02:00
Siva Durga Prasad Paladugu
a06c341faa net: zynq_gem: Add support for SGMII interface
Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:10:44 +02:00
Michal Simek
f17ea71d3a net: zynq: Change MDC setup for arm64
MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:54 +01:00
Mateusz Kulikowski
e7138b34b0 net: zynq_gem: Use shared wait_for_bit
Use existing library function to poll bit(s).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
2016-01-25 10:39:50 -05:00
Michal Simek
7bccc75a2b net: gem: Add driver dependencies to PHYLIB
Clear driver dependecies via Kconfig. Remove PHYLIB dependency from
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek
9d9211ac11 net: gem: Separate recv and free_pkt functions
Use core to call net_process_received_packet() instead of call inside
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek
da872d7c13 net: gem: Fix return value from recv
recv function should return 0 instead of frame_len not to
proceed the same packet again in core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek
bcdfef7a26 net: gem: Setup default phy address to -1
Undefined phy address is -1 not 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek
b8de29feae net: gem: Enable CTRL+C in wait_for_bit
Enable to break waiting loop at any time.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-07 10:14:29 +01:00
Michal Simek
3cdb1450de net: gem: Read information about interface from DT
Do not set interface via configs. Read information from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 10:14:28 +01:00
Michal Simek
6889ca7198 net: gem: Move driver to DM
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
  based on DM requirement
- Do not enable EMIO DT support by default

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-07 10:14:22 +01:00
Michal Simek
5a9284f7f5 net: gem: Fix miiphy_read name
Sync it with write function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
687d731263 net: gem: Remove zynq_gem_of_init()
This function was used for OF init before DM.
Remove this function as the part of move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
c8e29271b1 net: gem: Enable MDIO bus earlier
Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:05 +01:00
Michal Simek
90c6f2e21b net: gem: Check if priv->phydev is valid
Check return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
68cc3bd8b2 net: gem: Extract phy init code
Move phy init code out of zynq_gem_init. DM drivers are normally calling
this code from probe function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
64a7ead64b net: gem: Remove phydev variable
Resort code to use priv->phydev variable directly.
It will simplify move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
f2fc27684f net: gem: Change mii function not to use eth_device structure
Next step to move driver to driver model. Do not use eth_device
structure. Use private structure instead.
Add iobase to private structure to store gem iobase.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
3fac27243c net: gem: Change mdio_wait prototype to pass regs
Pass regs instead of dev because this will be chagned by
driver model.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
b904725a11 net: gem: Do not continue if phy is not found
Add return value for phy detection algorithm to stop init function when
phy is not found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:04 +01:00
Michal Simek
6777f38630 net: zynq: Fix MDC setting for zynq
Based on spec:
"MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
write operations)"
Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
which is above of 2.5MHz.
Using 48 divider will give us correct setting according spec
(111/48=2.31).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 14:03:05 +01:00
Michal Simek
2889659a55 net: zynq: Remove unused MDCCLKDIV2 macro
Driver cleanup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 14:03:05 +01:00
Michal Simek
242b15476c net: zynq: Fix mdc clock division setting for 100Mbit/s
Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 14:03:05 +01:00