Commit graph

19607 commits

Author SHA1 Message Date
Simon Glass
98bf740e7f x86: acpi: Don't show the UART address by default
This is useful when using Linux's earlycon since the MMIO address must be
provided on some platforms, e.g.:

   earlycon=uart8250,mmio32,0xddffc000,115200n8

However this is only for debugging, so don't show it by default.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:33 +08:00
Simon Glass
7f061e0d25 x86: acpi: Include the TPMv1 table only if needed
This table is not needed if a v2 TPM is in use. Add a condition to avoid
adding it when not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:32 +08:00
Simon Glass
1da448bb9f x86: Silence some logging statements
Quite a few log_info() calls are included in the x86 code which should use
log_debug() instead. Convert them to reduce unwanted output.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:32 +08:00
Simon Glass
d0147fe8a2 x86: fsp: Convert fsp_dram to use log_debug()
Use log_debug() instead of debug() in this file, to enable the extra
features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:32 +08:00
Simon Glass
9910fc183a x86: Set up Chrome OS to boot into developer mode
Set up a few fields necessarily to make Chrome OS boot without showing a
firmware error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
96d0aa9143 x86: Use CONFIG_CHROMEOS_VBOOT for verified boot
At present CONFIG_CHROMEOS is used to determine whether verified boot is
in use. The code to implement that is not in U-Boot mainline.

However, it is useful to be able to boot a Chromebook in developer mode
in U-Boot mainline without needing the verified boot code.

To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot
should be used, and CONFIG_CHROMEOS to indicate that the board supports
Chrome OS. That allows us to define CONFIG_CHROMEOS on coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
08059c9c02 x86: Define the Chrome OS GNVS region
It is not possible to boot Chrome OS properly without passing some basic
information from U-Boot. This applies even if verified boot is not being
used. Add a structure definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
18434aec1b acpi: Don't reset the tables with every new generation
At present if SSDT and DSDT code is created, only the latter is retained
for examination by the 'acpi items' command. Fix this by only resetting
the list when explicitly requested.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
01e3c9d2ec x86: acpi: Put the generated code first in DSDT
The current implementation for DSDT tables is not correct for the case
where there is generated code, as the length ends up being incorrect.
Also, we want the generated code to go first in the table.

Rewrite this piece to correct these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:30 +08:00
Simon Glass
2de4744dae x86: acpi: Allow the SSDT to be empty
If there is nothing in the SSDT we should not include it in the tables.
Update the implementation to check this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:30 +08:00
Simon Glass
a0ed800376 x86: Show the interrupt pointer with 'irqinfo'
It is useful for this command to show the address of the interrupt table.
Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
8bcfb7917a x86: nhlt: Fix a few bugs in the table generation
At present these tables do not have the correct header, and there is an
occasional incorrect value due to uninited data. Fix these bugs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
a87fff80ee x86: nhlt: Correct output of bytes and 16-bit data
At present these functions are incorrect. Fix them and add some logging
and checking to avoid future problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
d2cb7a22da x86: Allow putting some tables in the bloblist
At present all tables are placed starting at address f0000 in memory, and
can be up to 64KB in size. If the tables are very large, this may not
provide enough space.

Also if the tables point to other tables (such as console log or a ramoops
area) then we must allocate other memory anyway.

The bloblist is a nice place to put these tables since it is contiguous,
which makes it easy to reserve this memory for linux using the 820 tables.

Add an option to put some of the tables in the bloblist. For SMBIOS and
ACPI, create suitable pointers from the f0000 region to the new location
of the tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/
 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:28 +08:00
Simon Glass
f36e4c7d80 x86: Use if instead of #ifdef in write_tables()
Use if() to remove the extra build path in this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
cac9c6a38f x86: Add SMBIOS info for Coral
This is required by Chrome OS so that the audio and other unibuild
features work correctly. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
726310166b x86: coral: Drop the duplicate PCIe settings
These settings are included twice. The second lot are correct, so drop the
others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
dc0791d415 x86: Don't bother clearing global NVS
The bloblist guarantees that blobs are zeroed so there is no need to do
an additional memset(). Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
5019e201cc x86: acpi: Store the ACPI context in global_data
At present we create the ACPI context but then drop it after generation of
tables is complete. This is annoying because we have to then search for
tables later.

To fix this, allocate the context and store it in global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
38e498c3a2 x86: Allow writing tables to fail
At present write_tables() can fail but does not report this problem to its
caller. Fix this by changing the return type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
653554b40a x86: Add support for private files
Some boards need to include binary data into the image for use during the
boot process. Add a node for these.

An example is the audio-codec configuration used by some audio drivers on
Intel platforms. If no private files are provided, they will be omitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
dac7778d74 x86: Add a layout for Chrome OS verified boot
Add definitions for part of the vboot context used with verified boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
6571d87315 x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
9d20db0483 x86: Fix up driver names to avoid dtoc warnings
At present there are a lot of dtoc warnings reported when building
chromebook_coral, of the form:

   WARNING: the driver intel_apl_lpc was not found in the driver list

Correct these by using driver names that matches their compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Michal Simek
35b7ca768f arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig
CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be
able to use compile-time checks to reduce the number of build paths.

Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-04 10:13:44 -05:00
Tom Rini
7a8ac9df5d First set of u-boot-atmel fixes for 2021.01 cycle
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Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.01 cycle:

This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.
2020-11-02 09:01:28 -05:00
Eugen Hristev
ef8f34aea5 ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
2733e6fe5d ARM: dts: at91: sam9260ek: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
9f37458b30 ARM: dts: at91: sama5d3xmb: fix I2C bus unit address
w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
e0df9e846c ARM: dts: at91: gurnard: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
397a28604c ARM: dts: at91: at91sam9g25ek: fix I2C bus unit address
w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
6f668d2756 ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit address
w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
f56a0ca685 ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
a013df93e1 ARM: dts: at91: at91sam9261ek: fix SPI unit address warning
w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
7d0cad03d5 ARM: dts: at91: vinco: fix I2C warning bus unit address
w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Tom Rini
2c31d7e746 Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
2020-10-30 23:13:13 -04:00
Tom Rini
63d4607e03 of-platdata and dtoc improvements
sandbox SPL tests
 binman support for compressed sections
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Merge tag 'dm-pull-30oct20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

of-platdata and dtoc improvements
sandbox SPL tests
binman support for compressed sections
2020-10-30 15:24:30 -04:00
Jagan Teki
51656ae1d1 rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
d432975cec arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.

Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
39c8b2c72a rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.

PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
cf1b86a3ae rockchip: px30: Add EVB_PX30 Kconfig help
TARGET_EVB_PX30 can be possible to use other px30 boards.

Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.

This would help to track which boards are using EVB_PX30 config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Michael Trimarchi
9946bfd4a0 arm64: dts: rockchip: Add Engicam PX30.Core SOM
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features

PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.

Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
282ad86aaa arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
dfec5a4ec0 arm64: dts: rockchip: Add chosen node for ROCK-Pi N8
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.

This will help to get serial out messages.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:01 +08:00
Stefan Agner
ee68c83d0a rockchip: dts: tinker: remove unnecessary node
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Stefan Agner
cfac752dad rockchip: dts: tinker: move i2c node to shared device tree
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.

Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:06:13 +08:00
Simon Glass
4e28a259fd imx: mx6cuboxi: Disable thermal driver in SPL
This feature is incompatble with of-platdata since it uses the
U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are
those created by dtoc.

The driver is not used in SPL anyway, so exclude it from that build.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-10-29 14:42:56 -06:00
Simon Glass
bb44ebdd0f x86: apl: Take advantage of the of-platdata parent support
Now that parent devices are supported with of-platadata, we don't need the
messy code to fix up the parent pointers and allocations on Apollo Lake.
Put the code behind a condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29 14:42:18 -06:00
Simon Glass
d07f31aea0 x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOT
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI
and SPI flash are not enabled for TPL. Add a condition to fix this and
tidy up a build warning in the SPI-flash driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29 14:42:18 -06:00
Simon Glass
fbe27a54eb dm: Add a test for of-platdata parent information
Add a simple test that we can obtain the correct parent for an I2C
device. This requires updating the driver names to match the compatible
strings, adding them to the devicetree and enabling a few options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29 14:42:18 -06:00