Commit graph

69208 commits

Author SHA1 Message Date
Michal Simek
92dc921063 xilinx: Merge together BOOT_SCRIPT_OFFSET between MB and ARM
There is no reason not to use commong Kconfig by Microblaze too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
f2b0376010 xilinx: Remove additional newline in config files
Trivial fix.

Fixes: e519f03a18 ("cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
6a136e53f0 xilinx: Enable SF_TEST command for all ARM based platforms
Enable this command by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
483a31c8aa xilinx: zynq: Enable AES command
Enable AES command to be able to use it directly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
c2a2c83278 xilinx: zynq: Change types from u32 to uint32_t
Change parameter type to avoid compilation error:
In file included from ./tools/../lib/rsa/rsa-verify.c:23:0,
                 from tools/lib/rsa/rsa-verify.c:1:
include/u-boot/rsa-mod-exp.h:69:18: error: unknown type name ‘u32’; did you mean ‘__u32’?
 int zynq_pow_mod(u32 *keyptr, u32 *inout);
                  ^~~
                  __u32
include/u-boot/rsa-mod-exp.h:69:31: error: unknown type name ‘u32’; did you mean ‘__u32’?
 int zynq_pow_mod(u32 *keyptr, u32 *inout);
                               ^~~
                               __u32

Fixes: 37e3a36a54 ("xilinx: zynq: Add support to secure images")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
a0c26f74a9 xilinx: Enable FRU command for all ARM based platforms
Enable it by default for board detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
T Karthik Reddy
d388cedd46 xilinx: Add DDR base address to bootscript address
Add ram base address to scriptaddr env variable to make boot
script address to be a valid address when ddr base address changes.

This works properly if the first memory region is the region where uboot
runs. Also the solution was taken in respect of a lot of jtag script
putting u-boot script to certain address. For standard cases
bd->bi_dram[0].start is 0 all the time. Only for systems with DDR placed
out of this location it does calculation.

This is not the best solution and should be done differently in future but
enough for now till we don't have full solution ready yet.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
T Karthik Reddy
d93fbac512 arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.

With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
2fbdbee732 xilinx: zynqmp: Use tab for macro indentation
Trivial fix.

Fixes: fa793165da ("xilinx: zynqmp: refactor silicon name function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
07499daf50 xilinx: zynqmp: Do not check 0 as invalid return from snprintf
U-Boot SPL on ZynqMP is using CONFIG_SPL_USE_TINY_PRINTF which doesn't
return any return value and all the time returns 0. That's why
even correct snprintf was returning in SPL chip ID as "unknown".
Change checking condition and allow snprintf to return 0 which is according
manual patch successful return.
"If an output error is encountered, a negative value is returned."

Fixes: 43a138956f7e ("arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
16df2f1edb xilinx: zynqmp: Fix debug message in zynqmp_get_silicon_idcode_name()
Fix hex format from 0x%0X to 0x%0x to show correct numbers.

Fixes: fa793165da ("xilinx: zynqmp: refactor silicon name function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
Michal Simek
d026aa1de3 xilinx: zynqmp: Check return value from xilinx_pm_request()
xilinx_pm_request() can failed that's why also check return value.

Fixes: 050f10f103 ("xilinx: zynqmp: remove chip_id function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
f149b39ca3 xilinx: board: Add FRU decoder support
FMC cards are using FRU format for card identification. That's why add
support for this format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
4489e0aa9b xilinx: cmd: Add basic fru format generator
Idea is to have something what can be used for board bringup from
generic board perspective.

There is a violation compare to spec that FRU ID is ASCII8 instead of
binary format but this is really for having something to pass boot and
boot to OS which has better generating options.
Also time should be filled properly.

For example:
fru board_gen 1000 XILINX versal-x-prc-01-revA serialX partX

There is also support for revision field which is Xilinx specific field.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Siva Durga Prasad Paladugu
f1b97b5f18 xilinx: cmd: Add support for FRU commands
This patch adds support for fru commands "fru capture" and "fru display".
The fru capture parses the FRU table present at an address and stores in a
structure for later use. The fru display prints the content of captured
structured in a readable format.

As of now, it supports only common header and board area of FRU. Also, it
supports only English language code and ASCII8/BINARY formats.

fru_data variable is placed to data section because fru parser can be
called very early before bss is initialized. And also information needs to
be shared that's why it is exported via header.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
3e315f31cc xilinx: common: Add Makefile to common folder
There is no need to reference files in common folder back. Simply adding
Makefile to this folder does the job because this "common" location is
already wired in main Makefile.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
0b88e4516d microblaze: Enable i2c DM by default
Microblaze has been converted fully to DM that's why enabled DM for I2C
too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
7c553ac0ff xilinx: common: Protect board_late_init_xilinx()
Do not call board_late_init_xilinx() when BOARD_LATE_INIT is not enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
83594f3c01 xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board Kconfig
There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
13d1ca8742 spl: fdt: Record load/entry fit-images entries in 64bit format
The commit 9f45aeb937 ("spl: fit: implement fdt_record_loadable") which
introduced fdt_record_loadable() state there spl_fit.c is not 64bit safe.
Based on my tests on Xilinx ZynqMP zcu102 platform there shouldn't be a
problem to record these addresses in 64bit format.
The patch adds support for systems which need to load images above 4GB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 08:13:32 +01:00
Michal Simek
caa7fc2c57 spl: Use standard FIT entries
SPL is creating fit-images DT node when loadables are recorded in selected
configuration. Entries which are created are using entry-point and
load-addr property names. But there shouldn't be a need to use non standard
properties because entry/load are standard FIT properties. But using
standard FIT properties enables option to use generic FIT functions to
descrease SPL size. Here is result for ZynqMP virt configuration:
xilinx_zynqmp_virt: spl/u-boot-spl:all -82 spl/u-boot-spl:rodata -22 spl/u-boot-spl:text -60

The patch causes change in run time fit image record.
Before:
fit-images {
        uboot {
                os = "u-boot";
                type = "firmware";
                size = <0xfd520>;
                entry-point = <0x8000000>;
                load-addr = <0x8000000>;
        };
};

After:
fit-images {
        uboot {
                os = "u-boot";
                type = "firmware";
                size = <0xfd520>;
                entry = <0x8000000>;
                load = <0x8000000>;
        };
};

Replacing calling fdt_getprop_u32() by fit_image_get_entry/load() also
enables support for reading entry/load properties recorded in 64bit format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
ea836be1e7 spi: zynq_qspi: Use clk subsystem to get reference qspi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
b79a7030c3 spi: zynq_spi: Use clk subsystem to get reference spi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
6c9662df49 serial: pl01x: Add error value checking
There also a need to check return values to make sure that clocks were
enabled and setup properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 08:13:32 +01:00
Michal Simek
a03b594738 xilinx: board: Add support for additional card detection
The most of Xilinx evaluation boards have FMC connectors which contain
small eeprom for card identification. That's why read content of eeprom and
record it.
Also generate cardX_ variables for easier script handling.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
d61728c8e8 xilinx: board: Read the whole eeprom not just offset
Starts to use new way how eeproms should be referenced.
Reference is done via nvmem alias nodes. When this new way is specified
code itself read the eeprom and decode xilinx legacy format and fill struct
xilinx_board_description. Then based on information present there board_*
variables are setup.
If variables are saved and content can't be changed information is just
shown on console.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
305d31885f dm: core: Add support for getting node from aliases
Add support for getting a node/property from aliases.
The similar functionality is provided for chosen node and this
implemenatation is copy of it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
c94b44c64b spi: xilinx_spi: remove unused local variable
Remove unused variable 'count' which is causing warning while
compilation.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
30f47c0f1b dt-bindings: arm64: versal: Add clk and power headers
Add power and reset headers to be sources by Versal dtses.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
768622b1d7 arm64: zynqmp: Add support for saving sha3 key to different address
By default 48B sha3 hash value is written to srcaddr which is not the best
solution in case of that you want to use data for other operations. That's
why add key_addr optional parameters which enables to write 48B sha3 hash
value to specified address.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
0af9de9a90 arm64: zynqmp: Add support for SHA3 command
This patch adds support for SHA3 command. It takes data blob
as input and generates 48 bytes sha3 hash value.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
T Karthik Reddy
650d02ae77 arm64: zynqmp: Add support for RSA command
This patch adds support for RSA command, performs RSA encrypt &
RSA decrypt on data blob of key size.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Siva Durga Prasad Paladugu
8e4e914652 arm64: zynqmp: Add support for encryption and decryption on data blob
This patch adds support for encryption and decryption on a given data
blob using different key sources such as userkey(KUP), device key and
PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has
been introduced.

Command:
zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n"
	Encrypts or decrypts blob of data at src address and puts it\n"
	back to dstaddr using key and iv at keyaddr and ivaddr\n"
	respectively. keysrc values specifies from which source key\n"
	has to be used, it can be User/Device/PUF key. A value of 0\n"
	for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
	aesop value would specify the operationwhich can be 0 for\n"
	decrypt and 1 for encrypt(1) operation\n";

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
248fabc3ce arm64: zynqmp: Get rid of iommus/power-domains properties for SPL DT
SPL DT contains only nodes which are contain u-boot,dm-pre-reloc property.
iommu node is not this case that's why when DT is read DTC reports some
warnings.

$ dtc -I dtb -O dts dts/dt-spl.dtb >/dev/null
<stdout>: Warning (iommus_property): /amba/spi@ff0f0000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@ff160000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@ff170000:iommus: Could not get phandle node for (cell 0)

SPL also has an option to remove some DT properties which are useless for
SPL to make DT even smaller.
Default DT properties are pinctrl-0 pinctrl-names interrupt-parent
interrupts which are already removed.
The patch extends this list with iommus to get rid of above warnings.
Also power-domains unused properties can be removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
b15412f9a0 arm64: zynqmp: Enable cache command
Sometimes it is very useful to be able disable/enable cache that's why
enable commands for it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
e928406695 arm64: zynqmp: Enable FPGA loading from SPL
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
0d76b71d93 arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf
simple_itoa() is implemented only for !CONFIG_USE_TINY_PRINTF. Tiny printf
is normally used by SPL that's code which uses simple_itoa() has missing
reference. That's why refactor code by using on snprintf() instead of
strncpy()/strncat() combination. This change also descrease code size by
saving 24B based on buildman.

aarch64: (for 1/1 boards) all -22.0 rodata +2.0 text -24.0
         xilinx_zynqmp_virt: all -22 rodata +2 text -24
            u-boot: add: 0/0, grow: 0/-1 bytes: 0/-24 (-24)
              function                                   old     new   delta
              board_init                                 520     496     -24

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
f08d0c51b5 mailbox: zynqmp: Extend timeout for getting observation bit
In case of fpga loading (which can be huge) 100ms is not enough. That's why
extend timeout 10 times to wait maximum 1s to get ACK back.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Michal Simek
5690128f70 firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called
Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
means when fpga load is done from EL3 there is a need to swap it for PMUFW
to load bitstream.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 08:13:31 +01:00
Ashok Reddy Soma
5d5984c70e config: versal: Update mini u-boot timer clock to 100Mhz
Mini u-boot timer clock is not updated when u-boot is migrated from
emulator to silicon. Due to this slower clock of 2.72Mhz, delay() functions
are not working accurately. Update CONFIG_COUNTER_FREQUENCY to 100Mhz.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
Ashok Reddy Soma
90f06e9d20 arm64: versal: Update mini u-boot eMMC node parameters
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.

Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.

Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:31 +01:00
T Karthik Reddy
44d2be8d6a microblaze: Add support for distro boot
Add distro boot support for microblaze and enable jtag, qspi,
dhcp, pxe boot targets for distro boot.
Enable DISTRO_DEFAULTS config in microblaze defconfig and also
enable support for spi xilinx driver & spi vendors to access
spi flash by distro boot.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
T Karthik Reddy
ed0842d6c5 microblaze: Setup distro boot env variables at run time
Setup all the distro boot related environment variables at
run time. Add BOOT_SCRIPT_OFFSET config to microblaze board
Kconfig.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
T Karthik Reddy
d6242edcce microblaze: board: Check return value whlie saving env variables
Check and print warning if run time env variables are not saved.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
T Karthik Reddy
581d6a6da7 microblaze: trivial code fixes
Set proper indentation for env variables in microblaze header file.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
T Karthik Reddy
78efd7847c microblaze: Enable spi for microblaze
Enable SPI drivers and driver model for microblaze.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Michal Simek
e1303b2bc1 spi: xilinx_spi: Remove unused variable
Remove unused variable:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable]
  254 |  u32 reg, count, timeout;
      |                  ^~~~~~~

Fixes: 0c0de58f7b ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Michal Simek
b9ac6c0820 arm64: zynqmp: Enable EMMC boot
Enable EMMC boot commands to be able to change EMMC setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Michal Simek
bbe086a950 arm64: zynqmp: Add missing support for 9cg version
9cg version was supported before code refactoring. The patch is adding it
back.

Fixes: fa793165da ("xilinx: zynqmp: refactor silicon name function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Alexandre GRIVEAUX
bd897a0789 ARM: zynq: Add Z-turn board V5
Adding Z-turn board V5 to resolve the change between:

"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031

At this time the S25FL128SAGNFI003 doesn't work because of bug:

*** Warning - spi_flash_probe_bus_cs() failed, using default environment

zynq-zturn was checked on V5 board, same error.

Maybe Z-turn board have the same problem (board with W25Q128BVFIG).

Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00