53 commits

Author	SHA1	Message	Date
Lukas Auer	2a23ac6107	riscv: align mtvec on a 4-byte boundary ... The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2018-11-26 13:57:31 +08:00
Lukas Auer	c55309c091	riscv: fix inconsistent use of spaces and tabs in start.S ... start.S uses both tabs and spaces after instructions. Fix this by only using tabs after instructions. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>	2018-11-26 13:57:31 +08:00
Bin Meng	b5369c5813	riscv: Make start.S available for all targets ... Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>	2018-10-03 17:48:14 +08:00

Renamed from arch/riscv/cpu/ax25/start.S (Browse further)