Commit graph

6 commits

Author SHA1 Message Date
Axel Lin
52091ad146 spi: designware_spi: revisit FIFO size detection again
By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
  a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
     either 0 or 1 byte;
  b) FIFO size is incorrectly decreased by 1 which already done by meaning of
     TX Level register.

Fixes: 501943696e (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:42:49 +05:30
Simon Glass
19a25f672c dm: spi: Move the per-child data size to the uclass
This is common to all SPI drivers and specifies a structure used by the
uclass. It makes more sense to define it in the uclass.

Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:55 -07:00
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Axel Lin
501943696e spi: designware_spi: Fix detecting FIFO depth
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
   register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
   to test fifo == 257. In the case fifo is 257, it means the latest valid
   setting is fifo = 256. So after the for loop iteration, we should check
   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 15:52:27 +05:30
Stefan Roese
a72f80208d spi: designware_spi: Some fixes / changes
As suggested by Pavel, here some fixes to the designware SPI driver:

- Spelling fixes
- Comment for timeout added
- Removed n_bytes completely (bits_per_word is enough for this)
- Unput clock now not defined via macro. The function to
  get the clock value is now called directly from within the driver

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
5bef6fd79f spi: Add designware master SPI DM driver used on SoCFPGA
This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.

This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00