Commit graph

58338 commits

Author SHA1 Message Date
Simon Glass
4a4c5dd43f patman: Use items() instead of iteritems()
Python 3 requires this, and Python 2 allows it. Convert the code over to
ensure compatibility with Python 3.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:45 -06:00
Simon Glass
d141f6c1ca binman: Remove use of Set()
A new built-in set() is used in both Python 2 and 3 now. Move it to use
that instead of Set().

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:45 -06:00
Simon Glass
35343dc414 binman: Don't show errors for failed tests
An unfortunate new feature in Python 3.5 causes binman to print errors for
non-existent tests, when the test filter is used. Work around this by
detecting the unwanted tests and removing them from the result.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:45 -06:00
Simon Glass
2ca8468026 binman: Convert print statements to Python 3
Update all print statements to be functions, as required by Python 3.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:45 -06:00
Simon Glass
5a1af1dafe patman: Convert print statements to Python 3
Update all print statements to be functions, as required by Python 3.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:45 -06:00
Simon Glass
b1793a531e patman: Update cros_subprocess to use bytes
At present this function uses lists and strings. This does not work so
well with Python 3, and testing against '' does not work for a bytearray.
Update the code to fix these issues.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-10 16:52:43 -06:00
Tom Rini
ef8b7e045e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-i2c 2019-07-10 13:51:53 -04:00
Tom Rini
a52f1fe408 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-ubi
[trini: Migrate sama5d27_som1_ek_qspiflash/sama5d2_xplained_qspiflash
        for CONFIG_ENV_SECT_SIZE]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-10 13:18:54 -04:00
Masahiro Yamada
2ce6b82d34 ARM: uniphier: set {kernel, ramdisk, fdt}_addr_r at boot-time
The base of DRAM will be changed for the next generation SoC.
The addresses needed for booting the kernel should be shifted
according to the DRAM base.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:09 +09:00
Masahiro Yamada
7095678787 ARM: uniphier: set dram_base environment variable
The base of DRAM will be changed for the next generation SoC.

Set the base address to the 'dram_base' environment variable, which
will be useful for scripting.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:08 +09:00
Masahiro Yamada
3cc936d8ab ARM: uniphier: set loadaddr at boot-time
The base of DRAM will be changed for the next generation SoC.
To support it along with existing SoCs in the single defconfig,
set 'loadaddr' at boot-time by adding the offset to the DRAM base.

CONFIG_SYS_LOAD_ADDR is still hard-coded for compilation, but the
value from environment variable 'loadaddr' should be used.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:07 +09:00
Masahiro Yamada
72cd83ab81 ARM: uniphier: turn uniphier_set_fdt_file() into void function
For consistency with a function that will be added.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:07 +09:00
Masahiro Yamada
1f8357c3ab ARM: uniphier: remove CONFIG_SYS_SDRAM_BASE
The base address of DRAM was 0x80000000 for all the ARM SoCs of this
family in the past. It will be changed to 0x20000000 for a planned new
SoC. To support multiple SoCs by the single uniphier_v8_defconfig, the
base must be run-time determined.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:06 +09:00
Masahiro Yamada
34e29f7d94 ARM: uniphier: make mem_map run-time configurable
Currently, mem_map is hard-coded, and it worked well until the last
SoC. For a planned new SoC, the addresses of peripherals and DRAM
will be changed. Set it up run-time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:05 +09:00
Masahiro Yamada
df72534121 ARM: uniphier: make dram_init() more generic
Make this function work with any channel being empty.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:05 +09:00
Masahiro Yamada
6f47c99423 ARM: uniphier: make dram_init() independent of SG_MEMCONF
Currently, dram_init() code relies on the fact the DRAM size
configuration exists in the SG_MEMCONF register.

This will no longer be true for a planned new SoC, which will
replace SG_MEMCONF with a different register.

Refactor the hook in a more generic way.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:04 +09:00
Masahiro Yamada
34ded87506 ARM: uniphier: detect register base addresses run-time
Until the last SoC, the register addresses have been hard-coded because
they are always constant. For a planned new SoC, the register bases
will be completely changed. I insist on supporting multiple SoCs/boards
by a single defconfig (uniphier_v8_defconfig) since duplicating similar
defconfig files is a maintenance burden. The base addresses must be
fixed-up at run-time somehow.

Previously, the board init code identified the SoC by reading out the
SG_REVISION register. This is much easier than parsing DT.

You cannot do it any more because the base address of SG will be
changed. The SG_REVISION register exists to read out the SoC ID, but
you never know its address before identifying the SoC. Oh well.

So, the possible solution is to parse the DT, and find out the node
with "*-soc-glue" compatible string. Then, sg_base is set to the value
of the "reg" property. The sc_base is set up likewise.

It is worth noting a pit-fall. Having sc_base and sg_base in the global
scope will make the life easier, but the global variables are poorly
supported before the relocation. In fact, the .bss section overwraps
with DT. Allocating them in the .bss section would break DT. So, I gave
dummy initializers to assign them in the .data section.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:03 +09:00
Masahiro Yamada
739ba41d5a ARM: uniphier: de-couple SC macros into base address and offset
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.

Turn the SC_* macros into the offset from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:02 +09:00
Masahiro Yamada
d41b358fb3 ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.

Turn the SG_* macros into the offset from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:00 +09:00
Masahiro Yamada
c3d8f1e8e9 ARM: uniphier: detect SD boot mode
The planned new SoC supports the SD boot mode. Detect and display it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:59 +09:00
Masahiro Yamada
539d6e0dbc ARM: uniphier: make boot_is_swapped() code optional
The planned new SoC does not have SBC (System Bus Controller) block.
Make boot_is_swapped() an optional hook.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:58 +09:00
Masahiro Yamada
f7f390576d ARM: uniphier: check DT to determine whether to initialize SBC
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot initialize SBC
(System Bus Controller), which may not be really necessary.

Check the "socionext,uniphier-system-bus" node in DT run-time.
If and only if it is found and its "status" property is okay,
initialize the SBC block.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:57 +09:00
Masahiro Yamada
92d6524b4f ARM: uniphier: check DT to determine whether to use support card
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot tries to get access
to the devices on the support card, which may not actually exist.

Check the DT and search for the on-board devices run-time. If the
nodes are not found in DT, then disable the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:56 +09:00
Masahiro Yamada
9a2f0e5ccd clk: uniphier: add EMMC clock for LD11, LD20, and PXs3
I also added comments for NAND clocks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:55 +09:00
Masahiro Yamada
b521ea3958 ARM: uniphier: include <linux/io.h> from boot-device.c
This file calls readl(), so needs to include <linux/io.h>.
Currently, it relies on someone else including it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:54 +09:00
Masahiro Yamada
ef866f6f48 ARM: uniphier: use bool type for have_internal_stm parameter
This is boolean logic.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:53 +09:00
Masahiro Yamada
a179669c4e ARM: uniphier: clean up clk/Makefile
Now that 64-bit SoCs of this SoC family no longer support SPL,
this Makefile can be slightly simpler.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:52 +09:00
Masahiro Yamada
40c1a466ce ARM: uniphier: remove unused uniphier_ld11_boot_device_fixup()
The .boot_device_fixup() is only called by SPL.

Now that 64-bit SoCs of this SoC family no longer support SPL,
debug-uart-ld20.c is never compiled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:52 +09:00
Masahiro Yamada
7f283213a6 ARM: uniphier: remove empty #ifdef block
This is a remnant of commit f89d6133ee ("configs: move
CONFIG_SPL_TEXT_BASE to Kconfig").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:51 +09:00
Masahiro Yamada
47eb8add27 arm64: dts: uniphier: add reserved-memory for secure memory
[ Linux commit aa38571246c6ac279ebebd141157297bcb959d76 ]

The memory regions specified by /memreserve/ are passed to
early_init_dt_reserve_memory_arch() with nomap=false, so it is
not suitable for reserving memory for Trusted Firmware-A etc.

Use the more robust /reserved-memory node with the no-map property
to prevent the kernel from mapping it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:50 +09:00
Kunihiko Hayashi
9424ecd735 spi: Add SPI controller driver for UniPhier SoCs
Add SPI controller driver implemented in Socionext UniPhier SoCs.
This controller has the SPI master mode only.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2019-07-10 22:37:23 +09:00
Masahiro Yamada
92edfff6c6 ARM: uniphier_v8_defconfig: make 64bit SoC image position independent
For a planned new SoC in this SoC family, the base address of the
DRAM will be changed from 0x80000000 to 0x20000000.

The PIE support will be useful to maintain multiple similar SoCs
whose DRAM addresses differ.

Now CONFIG_SYS_TEXT_BASE is not important. I just set it to 0
to ensure CONFIG_POSITION_INDEPENDENT is working.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:37:23 +09:00
Masahiro Yamada
382de4a7e9 arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET
By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.

The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.

Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.

With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.

I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2019-07-10 22:37:23 +09:00
Tom Rini
b4944e2574 First set of u-boot-atmel features and fixes for 2019.10 cycle
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Merge tag 'u-boot-atmel-2019.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features and fixes for 2019.10 cycle

This includes the Atmel QSPI driver and support for the at91 boards.
This is the port of the driver from Linux, mostly done by Tudor Ambarus.
2019-07-09 08:17:12 -04:00
Chuanhua Han
ef6c26d338 rtc: pcf2127: Fixed bug with rtc settings and getting error time
The previous pcf2127 RTC chip could not read and set the correct time.
When reading the data of internal registers, the read address was the
value of register plus 1. This is because this chip requires the host
to send a stop signal after setting the register address and before
reading the register data.

This patch sets the register address using dm_i2c_write and reads
the register data using the original dm_i2c_xfer in order to generate
a stop signal after the register address is set, and fixes the bug of
the original read and write time.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-07-09 10:51:12 +02:00
Eugen Hristev
5dd4fa7fad configs: sama5d2_xplained: add support QSPI flash boot
The spi-nor flash resides on spi bus 1. Update the CONFIG_ENV_SPI_CS
and CONFIG_BOOTCOMMAND accordingly.

Based on original work by Wenyou Yang.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[tudor.ambarus@microchip.com: amend the commit message.]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
907f1da6ce configs: sama5d27_som1_ek: qspi: use common memory layout
Use the qspi memory layout defined in at91-sama5_common - it aligns
with the 8 Mbyte flash (sst26vf064b-104i/sn) available in sama5d27_som1_ek.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
ff352ac853 configs: sama5d27_som1_ek: add qspiflash_defconfig
Add the default config file of QSPI media. The config is based on
sama5d27_som1_ek_mmc_defconfig.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
9ee8e7aec7 configs: sama5d2_xplained: add qspiflash_defconfig
Add the default config file of QSPI media. The config is based on
sama5d2_xplained_mmc_defconfig.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Cyrille Pitchen
89e59c5602 ARM: at91: sama5: add common environment for QSPI
Use the same memory layout as we use for the NAND boot on the other boards.

QSPI flashes are present on the following boards:
sama5d2_xplained RevB:  32 Mbyte flash (mx25l3273fm2i-08g)
sama5d2_xplained RevC:   8 Mbyte flash (sst26vf064b-104i/sn)
sama5d27_som1_ek:        8 Mbyte flash (sst26vf064b-104i/sn)
sama5d2_ptc_ek:          8 Mbyte flash (sst26vf064b-104i/sn)

The 8 Mbyte limit is enough to cope with the memory layout used in the NAND
boot. rootfs exceeds the 8 Mbyte limit and will stay in eMMC in the
sama5d2_xplained case. The final scope is to use a single memory layout for
all boot medias.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus@microchip.com: change memory layout, add commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-07-09 09:26:43 +03:00
Cyrille Pitchen
4eeedd0306 ARM: dts: at91: sama5d2_xplained: fix QSPI0 node
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus@microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
e2c4dca97a configs: sama5d27_som1_ek: enable qspi controller and flashes
We use a sst spi-nor flash memory on sama5d27_som1_ek. Select
the others for testing purposes.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
8308e32c23 configs: sama5d2_xplained: enable qspi controller and flashes
We have a macronix spi-nor flash on sama5d2_xplained RevB and
a sst spi-nor flash on RevC. Select the rest for testing purposes.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Tudor Ambarus
24c8ff4684 spi: Add Atmel QuadSPI driver
Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-09 09:26:43 +03:00
Melin Tomas
d3826fb052 xilinx_xiic: Fix transfer initialisation
Prior to starting a new transfer, conditionally wait for bus to not
be busy.

Reinitialise controller as otherwise operation is not stable.
For reference, see linux kernel
commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer")

hs: Fixed DOS line endings
    added missing '\n'
    Fixed git commit description style

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2019-07-09 07:02:11 +02:00
Melin Tomas
5324e8ef6c xilinx_xiic: Fix fill tx fifo loop
Comparison should be against the actual message length, not loop index.

len is used for stopping while loop, pos is position in message.
stop should be sent when entire message is sent, not when
len and pos meet.

hs: fixed DOS line endings

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2019-07-09 07:02:11 +02:00
Ley Foon Tan
2d1e879c79 i2c: designware: Get clock rate from clock DM
Get clock rate from clock DM if CONFIG_CLK is enabled.
Otherwise, uses IC_CLK define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-07-09 07:02:11 +02:00
Jun Chen
e3b93dcee8 i2c: designware_i2c: Restore enable state after set speed
Before calling __dw_i2c_set_bus_speed(),
the I2C could already be set as ether enable or disable,
we should restore the original setting instead of enable i2c anyway.

This patch fix a bug happened in init function:
    __dw_i2c_init(){
            /* Disable i2c */
            ...
            __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
            writel(slaveaddr, &i2c_base->ic_sar);
            /* Enable i2c */
    }
In this case, enable i2c inside __dw_i2c_set_bus_speed() function
will cause ic_sar write fail.

Signed-off-by: Jun Chen <ptchentw@gmail.com>
2019-07-09 07:02:10 +02:00
Markus Klotzbuecher
a2257d378e ubispl: introduce separate CONFIG_UBI_SPL_SILENCE_MSG
This allows to silence ubi and ubispl individually.

Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kmpark@infradead.org>
2019-07-09 07:00:26 +02:00
Hamish Guthrie
6ea31cce0b ubispl: add support for loading volumes by name
The motivation is to use the UBI atomic volume rename functionality to
allow double copy software updates on UBI. To that end the SPL is
configured to always load the same volume name (e.g. "u-boot"),
whereas a software updater always installs into the secondary volume
"u-boot_r". After successful installation, these two volume names are
switched.

This extension is protected by #ifdefs as it will somewhat slow down
loading of volumes by id. This is because the code needs to disable
the optimization of ignoring all volume ids which are not
to-be-loaded, since these can only be resolved after attaching.

This adds two vtbl related functions from Linux, which are taken from
the same kernel version as the current main U-Boot UBI code (Linux 4.2
64291f7db5bd8).

Signed-off-by: Hamish Guthrie <hamish.guthrie@kistler.com>
Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Kyungmin Park <kmpark@infradead.org>
2019-07-09 07:00:25 +02:00