Commit graph

7 commits

Author SHA1 Message Date
Kumar Gala
2abbd31da6 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Dave Liu
c360ceac02 fsl-ddr: add the DDR3 SPD infrastructure
- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
2009-03-30 13:33:50 -05:00
Ed Swarthout
0ee84b88b7 Fix mpc85xx ddr-gen3 ddr_sdram_cfg.
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2009-03-09 17:46:09 -05:00
Poonam_Aggrwal-b10812
e1be0d25ec 32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572.
May  also be required for P10XX20XX platforms

Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
2009-02-16 18:06:03 -06:00
Dave Liu
ae5f943ba8 85xx: Fix the incorrect register used for DDR erratum1
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.

Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.

Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.

Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 17:29:37 -05:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Kumar Gala
2a6c2d7ab2 FSL DDR: Add 85xx specific register setting
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00