For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled. After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.
We also provide a per controller (rather than all) for some systems that
may have special requirements.
Finally, we refactor the code used by the P1022DS to utilize the new
generic code.
Based on patch by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference
clock for the audio codec, but by default both are disabled. Add a 'audclk'
hwconfig option that allows the user to choose which clock he wants.
The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48,
64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and
88200Hz.
Also configure a pin muxing to select some SSI signals, which will disable
I2C1.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.
Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The code to map SERDES configs to slot names is board specific and not
chip specific. Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Specifics:
1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
