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2 commits

Author SHA1 Message Date
Xingyu Wu
6c4b50e6de riscv: dts: jh7110: Add clock source from PLL 
Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-07-24 13:21:06 +08:00
Yanhong Wang
c04dfc7ac1 riscv: dts: jh7110: Add initial u-boot device tree 
Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
 2023-04-20 20:45:07 +08:00