Commit graph

12 commits

Author SHA1 Message Date
Stephen Warren
9614a1e963 tegra: enable NAND on Harmony
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:31 -07:00
Simon Glass
7cedd1811a tegra: fdt: Add NAND definitions to fdt
Add a flash node to handle the NAND, including memory timings and
page / block size information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:30 -07:00
Allen Martin
00a2749d7b tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Stephen Warren
b1b9e4ce3a tegra: ventana: add own device tree, enable USB
Add a device tree for Ventana; the Seaboard file no longer represents
the HW present on Ventana.

Enable USB on Ventana.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Stephen Warren
f3d93309c1 tegra: harmony: add device tree support
... to enable USB host support, which enables Ethernet support.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Stephen Warren
d5ebc937c9 tegra: Whistler board support
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:

E1120 motherboard
E1108 CPU board
E1116 PMU board

The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.

Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:17 +02:00
Anton Staff
c3ab91f064 tegra: fdt: Add keyboard definitions for Seaboard
Seaboard uses a QUERTY keyboard. We add key codes for this to
enable key scanning to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:40 +02:00
Simon Glass
d376e8d228 tegra: fdt: Add EMC data for Tegra2 Seaboard
This adds timings for T20 and T25 Seaboards, using the bindings found here:

http://patchwork.ozlabs.org/patch/132928/

We supply both full speed options for normal running, and half speed options
for testing / development.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:39 +02:00
Simon Glass
3682cc3d2c tegra: i2c: Select I2C ordering for Seaboard
Select the port ordering for I2C on Seaboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:50 +02:00
Simon Glass
1920172ec8 tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
We set up two USB ports, one of which can be host or device.
For some reason the kernel version does enable both ports.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
cd474cbae6 tegra: fdt: Add clock bindings for Tegra2 Seaboard
Add the definition of the oscillator clock frequency and the 32KHz clock.
The latter is provided by a PMIC on I2C which we don't actually use at
present, but we expect this definition to be used in the kernel and want
to keep our .dts the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
6710b5b5fd tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:47 +02:00