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4 commits

Author SHA1 Message Date
Alexey Brodkin
8b15010b1f arc: get rid of running_on_hw
ISS is obsolete now and nSIM is used for simulation instead.
In its turn nSIM properly handles baud-rate settings so get rid
of now useless check.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-04-11 10:20:30 -07:00
Alexey Brodkin
ef639e6f70 arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
    a) Use the same functions for all cache ops (D$ Inv/Flush)
    b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.

 [2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.

 [3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-07-01 17:17:27 +03:00
Alexey Brodkin
3fb8016360 arc: clean-up init procedure
Intention behind this work was elimination of as much assembly-written
code as it is possible.

In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.

It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.

Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
2015-04-03 09:47:49 +03:00
Alexey Brodkin
660d5f0d49 arc: move common sources in library
"reset.c" and "cpu.c" have no architecture-specific code at all.
Others are applicable to either ARC CPU.

This change is a preparation to submission of ARCv2 architecture port.

Even though ARCv1 and ARCv2 ISAs are not binary compatible most of
built-in modules still have the same programming model - AUX registers
are mapped in the same addresses and hold the same data (new featues
extend existing ones).

So only low-level assembly code (start-up, interrupt handlers) is left
as CPU(actually ISA)-specific. This significantyl simplifies maintenance
of multiple CPUs/ISAs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-01-15 22:40:49 +03:00
Renamed from arch/arc/cpu/arc700/cpu.c (Browse further)