Commit graph

65 commits

Author SHA1 Message Date
Vagrant Cascadian
a6f70a3d14 Fix spelling of "transferred".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:16 -04:00
Dinh Nguyen
a409a8b85e Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-02-04 12:43:21 +01:00
Siva Durga Prasad Paladugu
f72132673a fpga: xilinx: Check for substring in device ID validation
Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:53 +01:00
Dinh Nguyen
b00a21f088 arm: socfpga: set the fpga global bit to disable HPS to FPGA signals
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-01-16 07:07:22 +01:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Marek Vasut
bfa89d2ba8 arm: socfpga: Fix FPGA bitstream programming routine
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:04 +02:00
Michal Simek
e136eaeb4d fpga: xilinx: Show fpga info if defined
Show fpga_op->info even if desc->iface_fns is not defined.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-21 10:25:43 +01:00
Michal Simek
6cd68c811e fpga: xilinx: Check if fpga operations are defined
Ensure that operations are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-21 10:25:15 +01:00
Michal Simek
ebd322de43 fpga: Export fpga_get_desc for SPL
SPL needs to detect FPGA device which will be used
for loading bitstream.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-21 10:25:02 +01:00
Suriyan Ramasami
d455d8789d fs: API changes enabling extra parameter to return size of type loff_t
The sandbox/ext4/fat/generic fs commands do not gracefully deal with files
greater than 2GB. Negative values are returned in such cases.

To handle this, the fs functions have been modified to take an additional
parameter of type "* loff_t" which is then populated. The return value
of the fs functions are used only for error conditions.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
[trini: Update board/gdsys/p1022/controlcenterd-id.c,
drivers/fpga/zynqpl.c for changes]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:49:04 -05:00
Pavel Machek
230fe9b202 arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.
2014-10-06 17:46:50 +02:00
Marek Vasut
2012f238bd fpga: altera: Turn the switches into table lookup
Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:42 +02:00
Marek Vasut
fda915a4cf fpga: altera: Make altera_validate return normal values
Make the function return either 0 or -EINVAL, that is, normal
expected error codes and success codes instead of true/false
nonsense.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:42 +02:00
Marek Vasut
54c96b18a2 fpga: altera: Move altera_validate to the top
Move the function to the top of the file to avoid forward declaration.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:41 +02:00
Marek Vasut
4a4c0a5e9a fpga: altera: More indentation trimdown
Further improve the indentation in the rest of the file, where
the indentation is initially a bit less brutal. There is no
functional change in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:41 +02:00
Marek Vasut
5561a84148 fpga: altera: Clean up altera_validate function
Boldly go, where no programmer has gone before and just clean up
the indentation mayhem. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:41 +02:00
Marek Vasut
0ae16cbb40 fpga: altera: Clean up the printing and debug
Clean up the printf() statements and get rid of the PRINTF()
macro by replacing it with debug_cond().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:31:41 +02:00
Simon Glass
ddc94378db m68k: Fix warnings with gcc 4.6
Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by others, and there is an actual bug in the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:27:05 -04:00
Siva Durga Prasad Paladugu
1a897668ac fpga: Added support to load bit stream from SD/MMC
Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
       [<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
5b815c9c61 fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
7a78bd2679 fpga: Define bitstream type based on command selection
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Siva Durga Prasad Paladugu
3108185985 fpga: zynq: Use helper function zynq_validate_bitstream
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:05 +02:00
Siva Durga Prasad Paladugu
a0735a34f8 fpga: zynq: Use helper functions for zynq dma
Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:04 +02:00
Michal Simek
42a74a08eb fpga: zynq: Remove sparse warnings
Warnings:
drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer
drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:04 +02:00
Michal Simek
14cfc4f373 fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:13:59 +02:00
Michal Simek
f8c1be9816 fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:53 +02:00
Michal Simek
d9071ce0a8 fpga: virtex2: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:53 +02:00
Michal Simek
2a6e3869f2 fpga: spartan3: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:52 +02:00
Michal Simek
b625b9aef3 fpga: spartan2: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:52 +02:00
Alexey Brodkin
1ace402239 sizes.h - consolidate for all architectures
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 12:15:01 -05:00
Novasys Ingenierie
c83a35f652 fpga: zynq: Correct fpga load when buf is not aligned
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.

A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.

Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-06 10:08:03 +01:00
Masahiro Yamada
7b6af41ef3 drivers: descend into sub directories only when it is necessary
- Descend into drivers/fpga/ only when CONFIG_FPGA=y
  - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:30 -05:00
Michal Simek
b129e8cfb0 fpga: zynqpl: Do not place bitstream below 1MB
DMA doesn't work when src is placed below 1MB limit.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-11-06 09:15:12 +01:00
Jagannadha Sutradharudu Teki
ec4b73f09c fpga: zynqpl: Add dcache flush support
Buffers must be cache and dma aligned.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-06 09:15:12 +01:00
Masahiro Yamada
710f1d3d5f drivers: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:26:01 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Soren Brinkmann
5f93227ce0 fpga: zynqpl: Clear loopback mode during device init
Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.

In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:52:01 +02:00
Michal Simek
fd2b10b6d6 fpga: zynqpl: Add support for zc7100 device.
- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:01:50 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Michal Simek
6631db4773 fpga: Check device name against bitstream name
Ensure that wrong bitstream won't be loaded
to current device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:25 +02:00
Michal Simek
d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Michal Simek
23f4bd756d fpga: Change the first parameter in fpga_loadbitstream
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:20 +02:00
Michal Simek
52c2064476 cmd: fpga: Move fpga_loadbitstream to fpga.c
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:19 +02:00
Michal Simek
ee976c1b03 fpga: Fix debug message compilation error
CONFIG_FPGA in past was a bitfield where bits
were use for vendor identification.

This fix should be the part of this commit:
"Improve configuration of FPGA subsystem"
(sha1: 0133502e39)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:17 +02:00
Michal Simek
f6555d90c1 fpga: Clean coding style
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:40:53 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Stephan Gatzka
a99c040c33 FPGA: Cyclon II: Correctly reset the FPGA before configuration
Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.

This is also already done on other FPGA's, e.g. Stratix.

Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-10-29 14:21:20 -07:00
Thomas Weber
b199c6e2d7 Remove execute permissions from source files
Signed-off-by: Thomas Weber <weber@corscience.de>
2012-03-04 21:56:15 +01:00
Stefano Babic
33e1e01820 fpga: Spartan-3: let print the progress if configured
CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:20:12 +01:00
Stefano Babic
69de63e1f2 FPGA: drivers/fpga/ivm_core.c: GCC4.6 fix build warnings
Fix:
ivm_core.c: In function 'ispVMLCOUNT':
ivm_core.c:2105:16: warning: unused variable 'usByte'

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2011-11-16 20:49:40 +01:00