This commit adds support for 96Boards Dragonboard820C.
The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.
Features
- 4x Kyro CPU (64 bit) up to 2.15GHz
- USB2.0
- USB3.0
- ISP
- Qualcomm Hexagon DSP
- SD 3.0 (UHS-I)
- UFS 2.0
- Qualcomm Adreno 530 GPU
- GPS
- BT 4.2
- Wi-Fi 2.4GHz, 5GHz (802.11ac)
- PCIe 2.0
- MIPI-CSI, MIPI-DSI
- I2S
U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.
For detailed build instructions see readme.txt in the board directory.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII
PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE
when building. Fix the binman .dts file so that it doesn't use undefined
values.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
To support QSPI DM driver
- Add spi0 alias for qspi node. Which is used for bus number 0.
- Modify the n25q256a@0 compatible property to "spi-flash".
- Modify spi4 (gpio_spi) node to spi5
- Define DM SPI/QSPI related config to enable QSPI
Signed-off-by: Peng Fan <peng.fan@nxp.com>
BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate
function, ALT5 for ARM JTAG
Signed-off-by: Henry Zhang <henryzhang62@yahoo.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746
and STM32F769 discovery boards
There is a hardware issue on these boards, it misses a pullup on the GPIO line
used as card detect to allow correct SD card detection.
As workaround, cd-gpios property is not present in DT.
So SD card is always considered present in the slot.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This DT file comes from kernel v4.15-rc1
stm32f469-pinctrl.dtsi header has been updated with correct
STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
_ Add gpio compatible and aliases for stm32f429
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
All these files comes from kernel v4.15-rc1.
Update some header with correct STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The DB-88F6820-AMC connects ethernet@34000 and ethernet@70000 which are
labeled as eth2 and eth0 in armada-38x.dts. The ethernet@30000 (eth1) is
not used on the AMC board.
This eliminates the following bootup message
Device 'ethernet@70000': seq 0 is in use by 'ethernet@34000'
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Commit 8620f38409 ("dm: sunxi: Linksprite_pcDuino3: Correct polarity
of MMC card detect") claims that the Pcduino3 device tree had an
incorrect polarity for the card detect pin and thus changed the polarity
flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.
Actually the DT was correct since according to the mmc binding, a
combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low
polarity. But because the U-Boot driver lacks the code to look at the
cd-inverted property (unlike the Linux driver) it interpreted the
polarity of active-high. Thus, after that commit the DT is actually
wrong from the binding/Linux point of view.
To make both Linux and U-Boot interpret the DT in the same way, just
drop the left-over cd-inverted property. I've sent a Linux patch to
switch all sunxi DTs over to not using the cd-inverted property, so
eventually all sunxi boards in U-Boot will be consistent in not using
cd-inverted.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
and connectors are in the exact same position as on the Raspberry Pi B+.
Raspberry Pi B+ like peripherals supported on this board include:
- Power input through micro-USB connector (without USB OTG)
- Native 100 Mbps ethernet using the internal PHY, as opposed to
USB-based on the RPi
- 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
being connected through a USB 2.0 hub on the RPi
- TV and audio output on a 3.5mm TRRS jack
- HDMI output
- Micro-SD card slot
- Standard RPi B+ GPIO header, with the standard peripherals routed to
the same pins.
* 5V, 3.3V power, and ground
* I2C0 on the H3 is routed to I2C1 pins on the RPi header
* I2C1 on the H3 is routed to I2C0 pins on the RPi header
* UART1 on the H3 is routed to UART0 pins on the RPi header
* SPI0 on the H3 is routed to SPI0 pins on the RPi header,
with GPIO pin PA17 replacing the missing Chip Select 1
* I2S1 on the H3 is routed to PCM pins on the RPi header
- Additional peripherals from the H3 are available on different pins.
These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
In addition, there are a number of new features:
- Console UART header
- Consumer IR receiver
- Camera interface (not compatible with RPi)
- Onboard microphone
- eMMC expansion module port
- Heatsink mounting holes
This patch adds defconfig and dts files for this board. The dts file is
the same as the one submitted for inclusion in Linux, with some minor
revisions to match the dtsi file and old EMAC bindings in U-boot.
Since the OTG controller is wired to a USB host port, and the H3 has
proper USB hosts to handle host mode, the MUSB driver is not enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Without this propertiy, U-Boot will pop warning of 'USB phy type not
defined' when select CONFIG_HAS_FSL_DR_USB.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
This commit adds OMAP3 EVM devicetree files from Linux v4.15-rc3. Note
that this is the first addition of OMAP34XX devicetree files.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Enable sdmmc node in SPL and add it to boot order.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed commit tags:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since commit 999a78d5cf ("scripts/dtc: Update to upstream version v1.4.5-3-gb1a60033c110")
dtc warns about:
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing interrupt-parent for /soc/aips@50000000/serial@53fc0000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing interrupt-parent for /soc/aips@50000000/ccm@53fd4000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing interrupt-parent for /soc/aips@50000000/gpio@53fe4000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing interrupt-parent for /soc/aips@60000000/sdma@63fb0000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing interrupt-parent for /soc/aips@60000000/ethernet@63fec000
Fix this by adding a node for the tzic interrupt controller.
Copied from "<Linux>/arch/arm/boot/dts/imx53.dts"
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Commit 5248930ebf ("dm: imx: cm_fx6: Enable more driver model support")
enabled driver model support for USB, thereby effectively removing USB
support because the cm_fx6 devicetree in the U-Boot does *not* enable the
USB nodes.
Reinstate the USB support by syncing the devicetree with Linux whose
devicetree enables the USB nodes properly.
More precisely, use the devicetree found in Linux v4.15-rc1 with the
following two changes:
1) Remove the audio mux; the required dt-bindings header is not
present in the U-Boot.
2) Keep the usdhc3 MMC controller node currently present in the
U-Boot's devicetree to retain the ability to boot from MMC.
Fixes: 5248930ebf ("dm: imx: cm_fx6: Enable more driver model support")
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Order sun50i-h5-orangepi-prime.dts nodes in alphabetic
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlo3tMgACgkQykllyylKDCFQvQCfeFgaC/95gx9orLrHxpDx7s46
wwYAmwSoXn6hc9bEzgKIppQHblzfqGU6
=mscK
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.01-rc2-v2
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
This is the same patch as was done earlier.
Please look at Linux patch:
"arm64: zynqmp: Use only earlycon bootargs instead of full one"
(sha1: f3609c8d4af28b9cc22ca49bf8e529b582ec188c)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove overfetch, ratectrl, include-sg and src-issue dma properties.
Driver is not using them and they are also not documented in the binding
doc.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is enabling support for SPL QSPI boot.
First of all it is necessary to generate atf-spi.ub which is different
format than atf-uboot.ub (this can be made as legacy image too)
ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point
address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'`
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR
-e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin
atf-uboot.ub
./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR
-n "atf-for-qspi" -E -d bl31.bin atf-spi.ub
This patch is using this QSPI layout with offsets:
0 boot.bin
512k atf-ub
640k u-boot.bin
1280k u-boot.img
Which corresponding by writing these images(read from MMC)
mmcinfo
sf probe
load mmc 0 10000000 boot.bin
sf erase 0 +$filesize
sf write 10000000 0 $filesize
load mmc 0 10000000 atf-spi.ub
sf erase 0x80000 +$filesize
sf write 10000000 0x80000 $filesize
load mmc 0 10000000 u-boot.bin
sf erase 0xa0000 +$filesize
sf write 10000000 0xa0000 $filesize
load mmc 0 10000000 u-boot.img
sf erase 0x140000 +$filesize
sf write 10000000 0x140000 $filesize
For testing u-boot running in EL3 you can break atf-spi.ub like this:
sf probe
sf erase 0x80000 +4
Then u-boot.img is executed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This reference is needed for pinctrl driver where some signals can be
routed directly to platform management unit (PMU).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Update tegra to use binman for image creation. This still includes the
current Makefile logic, but a later patch will remove this. Three output
files are created, all of which combine
SPL and U-Boot:
u-boot-tegra.bin - standard image
u-boot-dtb-tegra.bin - same as u-boot-tegra.bin
u-boot-nodtb-target.bin - includes U-Boot without the appended device tree
The latter is useful for build systems where the device is appended later,
perhaps after being modified.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add bits to support yet another board, the R8A77995 D3 Draak.
The DT file is from Linux 4.15-rc1 , commit
b35334447513c14a4dd55a67c269a743d4a4824b .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add bits to support yet another board, the R8A77970 V3M Eagle.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add bits to support yet another SoC, the R8A77995 D3 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add bits to support yet another SoC, the R8A77970 V3M .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The TBS Tablet sports an LVDS display, an eMMC, an external SD, USB devices
and USB OTG.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
After updating dtc-1.4.5 version, there are too many warning.
This patch is to fix about exynos4 series.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This adds platform code for the Khadas VIM board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.
This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.
The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds platform code for the Libre Computer CC "Le Potato" board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.
This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.
The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
On the RK3399-Q7, we want to trigger a full platform reset (so the
various software stacks supported don't have to deal with the same
complexities over and over again) in case that anything other than a
power-on reset occurred.
To do so, this defines the /config/sysreset-gpio property and has it
point to a GPIO that will perform a power-on reset of the entire
platform.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
USB1 is connected to the on-module USB 3.0 hub and power to the hub
(actually it's a reset signal, modeled as a fixed regulator, that will
be released) should be enabled only during the first probing of the
device to avoid the hub from entering its low-power mode (where it
tries to attach on a fixed interval, but we always miss the timeslot
when U-Boot has the controller listening).
This adds a 'tsd,usb-port-power' stringlist to enable the
infrastructure in the board-specific usb_hub_reset_devices to find and
control the fixed regulator associated with control of the USB hub.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Add dts binding header for rk3128, files origin from kernel.
Series-Changes: 2
- fix i2c address
- add saradc and usb phy node
- emmc using fifo mode for there is no dma support in rk3128 emmc
- add some clock id in cru.h
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
In U-Boot, this device tree is compatible with both the Torpedo and
SOM-LV kits. Let's rename it in the device tree since the U-Boot code and
show a more generic OMAP3 name. The code auto detects between the two and
loads the proper DTB file for Linux. This would eliminate the SOM-LV showing
the name Torpedo during boot and hopefully eliminate some confusion.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
This node is needed to enable performance mode
when system frequency is set up to 200Mhz.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Stop using the old ad-hoc SH I2C driver and use the new RCar IIC
driver instead. The SH I2C driver should be deprecated and removed
eventually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is
needed very early and turn on the CONFIG_SYSCON to allow the PRR
driver to bind as a syscon uclass.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for ULCB to describe the hardware correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAloeqWoACgkQykllyylKDCHO1wCggsSgQqOPdCo207FqI3yj2p0E
MYkAoI1wKvQcjGJJY19YEC1r70Op8RNo
=BqNN
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
Enable watchdog in dts for zcu102.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch makes SMMU work by moving the iommus node under the dwc3 child
entry from parent node.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch uncomments snps,quirk-frame-length-adjustment which has
the value to adjust the SOF/ITP generated from the controller.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds OTG interrupt support in device tree. It will add
an extra interrupt line number dedicated to OTG events. This will
enable OTG interrupts to serve in DWC3 OTG driver.
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.
Also add address to unit name to avoid dtc warning
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for reading silicon revision using zynqmp nvmem
driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The AMS includes an ADC as well as on-chip sensors that can be used to
sample external voltages and monitor on-die operating conditions, such as
temperature and supply voltage levels.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch modifies the phy_zynqmp.c driver to use reset-controller
framework for asserting/de-asserting reset for High Speed modules.
Also fix documentation and dtsi.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch add the reset nodes in zynqmp.dtsi which are used by
reset-controller framework
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for zynqmp nvmem firmware driver.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added pin control support in device tree for zynqmp.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Generic dtsi file can't use the same mac address for all.
U-Boot read mac from eeprom in zcu102 case and for others random mac
address is generated.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dtc reports issues with it.
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Used defines rather than raw values for gpio configurations.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Some user space libraries reading platform compatible string and based
on that changing behavior. Mark revB board with revB string.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch disables the smmu and also removes the mmu-masters
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0]
Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so
SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0
Read ID/ Write ID for Data Port0 transfers = 1
Read ID/ Write ID for Non-Data Port1 transfers = 2
Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The correct register size is 0x10000, otherwise
it overlaps with other register space.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch will add names to the clocks used by GPU.
Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
PM callbacks are delivered to the NS OS. Let the PM driver handle the
IRQ and retrieve callback data from the secure HW.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0.
Tried lower values 5ms and 8ms and it worked fine with Debug Off.
But to accommodate PM Debug On case, 10 ms is required. With this
change, low power idle state is into effect more frequently.
Measured boot time with PM debugs On and Off. No change observed
compared to 100ms value.
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
Tested-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
