Commit graph

165 commits

Author SHA1 Message Date
Masahiro Yamada
4ce9957029 include: define CONFIG_SPL and CONFIG_TPL as 1
We are about to switch to Kconfig in the next commit.
But there are something to get done beforehand.

In Kconfig, include/generated/autoconf.h defines boolean
CONFIG macros as 1.

CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1.
Otherwise, when switching to Kconfig, the build log
would be sprinkled with warning messages like this:
  warning: "CONFIG_SPL" redefined [enabled by default]

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:02 -04:00
Shengzhou Liu
fb5368789a board/freescale: use generic board architecture for t2080qds and t2080rdb
Tested with NOR boot and NAND boot on T2080QDS and T2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-07-23 12:40:30 -07:00
Shengzhou Liu
09c2046ff6 board/t2080qds: enable sst and eon spi flash for nor boot
Remove unnecessary condition CONFIG_RAMBOOT_PBL to
have SST and EON SPI flash work in case of NOR boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Shengzhou Liu
40483e1e1d board/t2080qds: some update for ddr
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.

Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:06 -07:00
Liu Gang
e4911815cf powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.

The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:29:16 -05:00
Kim Phillips
3246584d19 mpc85xx: configs: remove c=ffe from default environment
AFAICT, c=ffe does nothing and was a typo from the original commit
d17123696c "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Edward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:27:05 -05:00
Shengzhou Liu
b19e288f47 board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Prabhakar Kushwaha
9307cbaba9 powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot size
U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Shengzhou Liu
9941cf781f powerpc/T208xQDS: add mtdparts suppport
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Shengzhou Liu
22cbf96434 powerpc/t208xqds: fix nor chip selection when nand boot
NOR flash is on CS1 instead of CS2 when NAND boot.
So correct NOR chip selection to CS1 from CS2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Zhao Qiang
dcf1d774bf QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Masahiro Yamada
e4536f8e37 freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}
Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI
and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2014-03-12 17:04:49 -04:00
Shengzhou Liu
6b7679c8d2 powerpc/t208xqds: fixup for t208xqds
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:41 -08:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Shengzhou Liu
254887a57e powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:01 -08:00
Renamed from include/configs/T2080QDS.h (Browse further)