boot from SDIO3.0 (mmc sdcard) first if it is plugged.
If mmc is not plugged try to boot from emmc if it is plugged.
If emmc is not plugged then try to boot from nvme.
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Make NVMe and USB target boot devices on the StarFive VisionFive 2 board.
The boot devices are sorted by decreasing device speed.
CONFIG_PCI_INIT_R=y is set via [1]. 'start usb' is added to CONFIG_PREBOOT
by the same patch.
[1] [PATCH v1 1/2] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2
https://lore.kernel.org/u-boot/TY3P286MB2611C9AD6E5BB3756A959E89981FA@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
