Commit graph

30003 commits

Author SHA1 Message Date
Alison Wang
036f3f3379 arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Linus Walleij
d77447fdb1 serial: pl01x: fix PL010 regression
commit aed2fbef5e
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.

Fix this by inlining the missing write to the baud control
register.

Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.

Tested on the Integrator/AP hardware.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-21 10:05:42 -04:00
Andrey Skvortsov
a436d61279 kconfig: remove duplicated CMD_DNS option
two CMD_DNS options were added by commit 60296a835c ("commands: add more
command entries in Kconfig")

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 10:03:54 -04:00
Marek Vasut
b284d268af arm: socfpga: spl: Add stub sdram.h
Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still
need to be able to compile the codebase. Introduce stub functions which
temporarily supplement the missing SDRAM setup functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:37:12 +02:00
Marek Vasut
96bfdf01ca spi: Add Cadence QSPI controller Kconfig entry
Add Cadence QSPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:38 +02:00
Marek Vasut
67d7a9d643 spi: Add Designware SPI controller Kconfig entry
Add DWC SPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:36 +02:00
Dinh Nguyen
8b73dda86b arm: socfpga: spl: update peripheral pll for dev kit
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
0ef44d1150 arm: socfpga: spl: add board_init_f to SPL
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
a74732b611 arm: socfpga: spl: Add s_init stub
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still branching to s_init(), we need stub function for now, until
lowlevel_init() morphs into s_init().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
3c38de5464 arm: socfpga: fix uart0 pin mux configuration
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration"
incorrectly set the muxing for UART0 on the Cyclone V DK.

This fixes it up so UART0 is working again.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
9ad3a4ace2 arm: socfpga: spl: Add SDRAM check
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
18ad2de4b2 arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc
We need to adjust the SYS_INIT_RAM_SIZE to have room for the
SPL_MALLOC_SIZE.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
a717b811ff arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
9cfafc7551 arm: socfpga: spl: Use common lowlevel_init
For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the
SoCFPGA lowlevel_init.S file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
89ba82479e arm: socfpga: spl: printout sdram size
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
37ef0c70d3 arm: socfpga: spl: add sdram init and calibration
Add a call to checkboard along with sdram intilialization and calibration.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:16 +02:00
Dinh Nguyen
08e463ee8a arm: socfpga: spl: allow bootrom to enable IOs after warm reset
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:16 +02:00
Dinh Nguyen
9fd565dbe7 arm: socfpga: spl: Add call to timer_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:16 +02:00
Dinh Nguyen
0812a1d3e5 arm: socfpga: spl: enable sdram, timer and uart
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:16 +02:00
Dinh Nguyen
c218f85ea1 arm: socfpga: add functions to bring sdram, timer, and uart out of reset
These functions will be needed for use by the SPL for enabling the
console and sdram initialization.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2015-04-21 12:23:16 +02:00
Dinh Nguyen
6868160ab1 arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:16 +02:00
Tom Rini
91528821d9 Merge branch 'master' of git://git.denx.de/u-boot-net 2015-04-20 20:16:21 -04:00
Bin Meng
523bb66f5a net: pch_gbe: Fix pch_gbe device name
The name "pch_gbe.%x" exceeds the limit of the name in the
'struct eth_device'. Rename it as just "pch_gbe".

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-20 17:57:13 -05:00
Michal Simek
9ce1edc8d0 net: gem: Use correct type for casting
Use phys_addr_t which is used in function prototype
in system.h.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-20 17:57:13 -05:00
Shengzhou Liu
5707d5ffd4 net/phy: fixup for get_phy_id
commit 3c6928fd7b "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-04-20 17:57:13 -05:00
Luca Ellero
c6a40f6e51 net: phy: micrel: add support for KSZ8081MNX
This patch adds a support for KSZ8081MNX in MII mode.

Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
Acked-by: Pavel Machek <pavel@denx.de>
2015-04-20 17:57:12 -05:00
Tim James
a095f047eb mii: add read-modify-write option to mii command
When accessing PHY registers it is often desirable to only update
selected bits, so it is necessary to first read the current value
before writing back an modified value with the relevant bits
updated.

To simplify this and to allow such operations to be incorporated
into simple shell scripts propose adding a 'modify' option to the
existing mii command, which takes a mask indicating the bits to
be updated in addition to a data value containing the new bits,
ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>).

Signed-off-by: Tim <tim.james@macltd.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tim <tim.james@macltd.com>
2015-04-20 17:57:12 -05:00
Joe Hershberger
a60de1ee7f Update MAINTAINERS and git-mailrc for net
Update to my corporate email and make the supported filter and aliases
more accurate.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-20 17:57:12 -05:00
Thierry Reding
744152f8cf net: rtl8169: Build warning fixes for 64-bit
Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.

Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-20 17:57:11 -05:00
Codrin Ciubotariu
3cee138892 net: phy: realtek: Disable interrupt on Realtek Ethernet PHY drivers
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-20 17:57:11 -05:00
Tom Rini
dd9958a3f4 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-04-20 17:12:45 -04:00
Scott Wood
221fbd229c powerpc/mpc8641hpcn: Move environment to avoid conflict
U-Boot on this board grew a long time ago past the 384 KiB that
it reserves for the U-Boot image, before the environment.  Thus,
saveenv overwrites the U-Boot image and bricks the board.

I tried to find out when U-Boot grew beyond this point, but there is a
long stretch in the history where this board did not build -- and
AFAICT when it did fit in 384 KiB, it was missing vital features such
as fdt support.  Turning off CONFIG_VIDEO was not enough to make it
fit.  Thus, I don't think we have any choice other than to move the
environment.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:30 -07:00
Shengzhou Liu
747aedafa0 board/t2080rdb: enable CONFIG_PHY_AQUANTIA
CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:30 -07:00
Scott Wood
d87a2ad108 powerpc/mpc85xx: Remove some dead code
U-Boot does not have system calls (the services it exposes to
standalone commands use a different mechanism), so the syscall handler
is dead code.  It's also broken code, as it assumes it is located at
0xc00 -- while even before the patch to stop relocating exception
vectors to 0, U-Boot had the syscall at 0x900.

The critical and machine check return paths are never called -- the
regular exception return path is used instead, which works because
xSRR0/1 have already been saved and can be restored via the regular
SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck
inside another exception prolog/epilog).

Also remove a few other small unused functions.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Scott Wood
96d2bb952b powerpc/mpc85xx: Don't relocate exception vectors
Booke does not require exception vectors to be located at address zero.
U-Boot was doing so anyway, simply because that's how it had been done
on other PPC.  The downside of this is that once the OS is loaded to
address zero, the exception vectors have been overwritten -- which
makes it difficult to diagnose a crash that happens after that point.

The IVOR setup and trap entry code is simplified somewhat as a result.

Also, there is no longer a need to align individual exceptions on 0x100
byte boundaries.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Shengzhou Liu
4913229ed6 powerpc/t2080rdb: update ddr to support 1866MT/s
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB.
Enable CONFIG_CMD_MEMTEST as well.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Chunhe Lan
a8efe79c0b T4240RDB: Enable CONFIG_SYS_CORTINA_FW_IN_NOR config
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR
to define that firmware of cortina driver is stored in the
nor flash.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Ying Zhang
e5abb92c0b board/t208xrdb: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Shengzhou Liu
9ca0d35f24 powerpc/t2080: enable erratum_a007186 for t2080 rev1.1
T2080 rev1.1 also needs erratum a007186.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Alexander Graf
e834975b4b qemu-ppce500: Add support for 64bit CCSR map
QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
to reside in higher address space.

Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
a function to dynamically evaluate the CCSR region's position in physical
address space, we never used it. Plus we forgot to support 64bit physical
addresses.

This patch fixes that mishap, making u-boot work fine with latest QEMU again.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Curt Brune
d7c865bdf2 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register
According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section 9.4.1.8 of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source
       synchronously.

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit
457caecdbc.

Testing Done:

Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.

Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:28 -07:00
Tom Rini
1733259d25 Merge branch 'master' of git://git.denx.de/u-boot-video 2015-04-20 09:13:52 -04:00
Heiko Schocher
fc1a79d95e video, lg4573: add support for the lg4573 display
Signed-off-by: Heiko Schocher <hs@denx.de>
2015-04-20 09:47:28 +02:00
Heiko Schocher
cb9f8e6a73 video, ipu: make ldb clock frequency overwritable through board code
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.

This should be removed, if a clock framework is availiable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2015-04-20 09:36:59 +02:00
Heiko Schocher
0ced25beb5 video, ipu: make ldb_clock configurable
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2015-04-20 09:34:45 +02:00
Sjoerd Simons
791a9f67f4 sandbox: add config_distro_defaults and config_distro_bootcmd
Make the sandbox setup more generic/examplary by including
config_distro_defaults.h and config_distro_bootcmd.h.

Among other things this makes it easy to test whether images will boot
though with the standard distro bootcmds by running e.g:
  u-boot -c 'host bind 0 myimage.img ; boot'

By default there are 2 target host devices to emulate device with
multiple storage devices (e.g. internal ("host 0") and external
("host 1") and verify that the prioritization and fallbacks do work
correctly.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-19 14:45:58 -06:00
Sjoerd Simons
f96d0b8149 config: Add default client arch defines for intel architectures
Define default PXE client architecture identifiers for IA32 (0x0 aka
Intel x86PC) and Intel x86-64 (0x9 aka EFI x86-64).

This prepares for usage for config_distro_defaults in the sandbox
architecture

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2015-04-19 14:45:58 -06:00
Sjoerd Simons
4a0bd1020f pxe: Ensure all memory access is to mapped memory
Properly map memory through map_sysmem so that pxe can be used from the
sandbox.

Tested in sandbox as well as on jetson-tk1, odroid-xu3, snow as peach-pi
boards

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-19 14:45:58 -06:00
Sjoerd Simons
d0bce0d1cb config_distro_bootcmd.h: Add shared block definition for the host interface
Define the common shared block environment for the host interface in
preperation for the sandbox build to use config_distro_bootcmd.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2015-04-19 14:45:58 -06:00
Sjoerd Simons
9b97b6ba24 sandbox: Implement host dev [device]
A common pattern to check if a certain device exists (e.g. in
config_distro_bootcmd) is to use: <interface> dev [device]

Implement host dev [device] so this pattern can be used for sandbox host
devices.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-19 14:45:57 -06:00