Commit graph

40 commits

Author SHA1 Message Date
Siva Durga Prasad Paladugu
74ba69db35 arm64: zynqmp: Make chip_id routine to handle based on el.
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
f52bf5a3dd arm64: zynqmp: Make chip_id a global routine()
This patch makes chip_id() as a global routine so that
it can be used in other places as required.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
db3123b40d arm64: zynqmp: Modify chip_id routine to get either idcode or version
This patch modifies the chip_id routine to get either idcode or
silicon version based on the argument received.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
4b5b0fcd21 arm64: zynqmp: Dont write to system timestamp generator
Remove incorrect code of writing to system timestamp
counter registers. This register writes does nothing
and can be removed.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
a076789efe arm64: zynqmp: Define a way to intialize TCM
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
fb4000e871 arm64: zynqmp: Check pmufw version
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:13 +02:00
Siva Durga Prasad Paladugu
e0752bc184 arm64: zynqmp: Define routines for mmio write and read
Define routines of mmio write and read functionalities
for zynqmp platform.

Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.

Also make invoke_smc as global so that it can be reused in
multile places where ever possible.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:06 +02:00
Stefan Herbrechtsmeier
eff55c55c7 net: zynq: Add clk framework support to zynq ethernet driver
If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Michal Simek
509d4b9545 ARM64: zynqmp: Generate handoff structure for ATF
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.

Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:22:05 +01:00
Siva Durga Prasad Paladugu
a765bdd1cb net: zynq_gem: Use clock driver for ZynqMP
Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:12 +01:00
Michal Simek
49c4c78e70 block: Move ceva driver to DM
This patch also includes ARM64 zynqmp changes:
- Remove platform non DM initialization
- Remove hardcoded sata base address

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-12-20 09:15:27 +01:00
Tom Rini
361a879902 Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"
This reverts commit 3edc0c2522, reversing
changes made to bb135a0180.
2016-12-09 07:56:54 -05:00
Michal Simek
8814c03853 block: Move ceva driver to DM
This patch also includes ARM64 zynqmp changes:
- Remove platform non DM initialization
- Remove hardcoded sata base address

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Series-to: sjg, agraf@suse.de
Series-cc: uboot
Series-version: 4
Series-changes: 2
- make ceva_init_sata static
- Move SATA_CEVA to defconfig
- Initalized max_lun and max_id platdata

Series-changes: 3
- Extend Kconfig help description
- sort dm.h
- Remove SPL undefinition from board file
- Fix Kconfig dependecies
2016-12-08 09:23:48 +01:00
Michal Simek
2661081c30 ARM64: zynqmp: List secondary software boot modes
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-12-02 14:35:57 +01:00
Siva Durga Prasad Paladugu
e1992276c3 ARM64: zynqmp: Add support for SD1 with level shifters bootmode
Add support for SD1 with level shifters bootmode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:28:05 +01:00
Michal Simek
48255f5276 ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
3373a52283 ARM64: zynqmp: Add USB boot mode
Add USB boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
7f491d7b30 ARM64: zynqmp: Force certain bootmode for SPL
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
23ffd36a52 ARM64: zynqmp: Remove get_uart_clk()
ZynqMP will use reading clock freq directly from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-07-22 14:04:41 +02:00
Michal Simek
e6a9ed04e7 ARM64: zynqmp: Add SPL support support
Support RAM and MMC boot mode in SPL also with SPL_FIT images.

In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
 aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
 mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
 -d bl31.bin atf.ub
 cp spl/boot.bin <sdcard fat partition>
 cp atf.ub <sdcard fat partition>
 cp u-boot.bin <sdcard fat partition>

2) Boot flow with full U-Boot(EL3):
 cp spl/boot.bin <sdcard>
 cp u-boot*.img <sdcard>

3) emmc boot mode
 dd if=/dev/zero of=sd.img bs=1024 count=1024
 parted sd.img mktable msdos
 parted sd.img mkpart p fat32 0% 100%
 kpartx -a sd.img
 mkfs.vfat /dev/mapper/loop0p1
 mount /dev/mapper/loop0p1 /mnt/
 cp spl/boot.bin /mnt
 cp u-boot.img /mnt
 cp u-boot.bin /mnt
 cp atf.ub /mnt
 umount /dev/mapper/loop0p1
 kpartx -d sd.img
 cp sd.img /tftpboot/

 and program it via u-boot
 tftpb 10000 sd.img
 mmcinfo
 mmc write 10000 0 $filesize
 mmc rescan
 mmc part
 ls mmc 0

psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.

The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Michal Simek
e832a142b9 ARM: zynq: Remove unused SPI base addresses
Remove unused macros. Adresses are taken from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
2016-02-22 16:20:59 +01:00
Siva Durga Prasad Paladugu
78cb965af0 zynqmp: nand: Add Nand driver support for zynqmp
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-12 17:27:28 -06:00
Michal Simek
af813acd48 ARM64: zynqmp: Add support for SD1 boot mode
SD1 boot mode is using different bootmode values.
Add support for this mode used on DC1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Siva Durga Prasad Paladugu
0a5bcc8c0d ARM64: zynqmp: Modify the SD and QSPI bootmode values
Modify the SD bootmode value to 0x3 as per latest
spec. Also add new boot mode QSPI 32 bit boot mode

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
0785dfd8a7 ARM64: zynqmp: Use the same U-Boot version with/without ATF
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
d9ae52c8f0 zynq: sdhci: Move driver to DM
Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
769afa54c6 ARM: zynq: Remove unused SERIAL macros for serial_zynq
Remove unused macros when driver was moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
e490ad25eb ARM64: zynqmp: Sync zynq_sdhci_init() declaration
This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
 int zynq_sdhci_init(phys_addr_t regbase)
     ^
In file included from drivers/mmc/zynq_sdhci.c:14:0:
./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration
of ‘zynq_sdhci_init’ was here
 int zynq_sdhci_init(unsigned long regbase);
     ^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-07 08:17:54 -05:00
Siva Durga Prasad Paladugu
16fa00a711 zynqmp: usb: Add usb dwc3 driver support for zynqmp
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19 11:27:30 +02:00
Michal Simek
cb526c1c88 zynqmp: Enable U-Boot run in EL3
Enable Secure IOU setup to enable U-Boot to run in EL3 without
setting from ATF.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19 11:23:13 +02:00
Michal Simek
6fe6f13509 ARM: zynqmp: Wire up SATA for the board
Enable SATA for the ZynqMP targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
cb7ea82059 ARM: zynqmp: Wire up ethernet controllers
Wire up ethernet controllers and enable MII and BOOTP options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
225bf9aa65 zynqmp: Add support for IP detection via SLCR
SLCR can be used for IP configuration setting.
Add SLCR skeleton to enable run time checking.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:20 +02:00
Michal Simek
31137acb27 zynqmp: Enable SDHCI0 options
Enable SDHCI0 for zynqmp.
Add empty gpio.h because of sdhci requirement.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-29 11:19:04 +02:00
Siva Durga Prasad Paladugu
48d7260d19 zynqmp: Add SPI driver support for ZynqMP
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-29 11:19:04 +02:00
Siva Durga Prasad Paladugu
2594e03c64 zynqmp: i2c: Enable i2c driver for zynqMP
Enable the i2c driver for ZynqMP
Also enable the eeprom for read and writes
to eeprom on ZynqMP
ZynqMP uses the same i2c controller as in Zynq

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-29 11:19:04 +02:00
Michal Simek
39c56f55be zynqmp: Add support for EMMC bootmode
Add support for EMMC bootmode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-29 11:19:04 +02:00
Michal Simek
16247d28d5 zynqmp: Add support for emulation platform - Veloce
Add support for Veloce - zynqmp emulation platform.
Platform doesn't support SDHCI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-29 11:19:03 +02:00
Michal Simek
5cb2420037 zynqmp: Add support for R5 sw loading
Add support for loading sw for R5 with enabling for zynqmp.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-04-29 11:19:03 +02:00
Michal Simek
84c7204bd1 arm64: Add Xilinx ZynqMP support
Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-02 18:41:54 +01:00