The latest SOM specification doesn't enforce certain MIO lines allocated
for ethernet or ethernet controller itself. That's why remove comment about
it which is likely there from early version of specification.
Also removed the same comment from pinctrl node. It is clear that it has to
be defined for different carrier cards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9406377bf2c391ac0200670511bd6b0edb097c96.1676880543.git.michal.simek@amd.com
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb gorup pins.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
Use ethernet-phy-id compatible string to properly describe phy reset on
kv260 boards. Previous description wasn't correct because reset was done
for mdio bus to operate and it was in this case used for different purpose
which was eth phy reset. With ethernet-phy-id phy reset happens only for
the phy via phy framework.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/73b64f1a2b873b4e26bd2b365364bdf313794ae2.1645629459.git.michal.simek@xilinx.com
With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs.
Also setup proper bus width for SD cards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/d9f80b2551bd246c3d7ecb09b516806c8dc83ed9.1645629459.git.michal.simek@xilinx.com
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DT files have been added this year but forgot to update it that's why do it
in separate patch now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dtc supports new sugar syntax which is easier compare to previous one
that's why also covert overlays for SOM to it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.
Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
