Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
The editenv command can be used to edit an environment variable.
Editing an environment variable is useful when one wants to tweak an
existing variable, for example fix a typo or change the baudrate in the
'bootargs' environment variable.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Previously setenv() would only delete an environment variable if it
was passed a NULL string pointer as a value. It should also delete an
environment variable when it encounters a valid string pointer of
0-length.
This change/fix is generally useful and is necessary for the upcoming
"editenv" command.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
If the 'buf' parameter is a non-0-length string, its contents will be
edited. Previously, the initial contents of 'buf' were ignored and the
user entered its contents from scratch.
This change is necessary to support the upcoming "editenv" command but
could also be used for future commands which require a user to modify
an existing string.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Previously, passing readline() or readline_into_buffer() a NULL 'prompt'
parameter would result in puts() printing garbage when
CONFIG_CMDLINE_EDITING was enabled.
Note that no board currently triggers this bug. Enabling
CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in
the bug appearing. This change is only intended to prevent someone
from running into this issue in the future.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Add missing newline.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Setup QE pin multiplexing for USB function, configure needed BCSRs
and add some fdt fixups.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
To make QE UART usable by Linux we should setup pin multiplexing
and turn UCC2 Ethernet node into UCC2 QE UART node.
Also, QE UART is mutually exclusive with UART0, so we can't enable
it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype
board with eSDHC in 1- or 4-bits mode.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few
qe_iop entries to actually enable SPI1 on these boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch sets memory window for Serial RapidIO on MPC8569E-MDS
boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.
Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).
So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
address in SDRAM. Previously, secondary cores were put into spin
loops in the 0xfffffxxx address range which required that boot page
translation was always enabled while cores were in their spin loops.
- Allow the TLB window that the primary core uses to access the
secondary cores boot page to be placed at any address. Previously, a
TLB window at 0xfffff000 was always used to access the seconary cores'
boot page. This TLB address requirement overlapped with other
peripherals on some boards (eg XPedite5370). By default, the boot
page TLB will still use the 0xfffffxxx address range, but this can be
overridden on a board-by-board basis by defining a custom
CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page
remains in use while U-Boot executes. Previously it was only
temporarily used, then restored to its initial value.
- Allow Boot Page Translation to be disabled on bootup. Previously,
Boot Page Translation was always left enabled after secondary cores
were brought out of reset. This caused the 0xfffffxxx address range
to somewhat "magically" be translated to an address in SDRAM. Some
boards may not want this oddity in their memory map, so defining
CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
the secondary cores are initialized.
These changes are only applicable to 85xx boards with CONFIG_MP defined.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The data being modified was in NOR flash which caused the crash.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX
constant. With multi-serial support, the CONS_INDEX may no longer
represent actual console, so we should try to extract port number
from the current stdio device name instead of always hard-coding the
constant value.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot crashed on the last instruction:
int parse_stream_outer(struct in_str *inp, int flag)
{
effa4784: 94 21 ff 38 stwu r1,-200(r1)
effa4788: 7c 08 02 a6 mflr r0
effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc>
effa4790: 7d 80 00 26 mfcr r12
effa4794: 13 c1 b3 21 evstdd r30,176(r1)
...which is a SPE instruction, although -mno-spe was used.
tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version
powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3
Seems to be a known issue (since 2008-04?!)
Googled some, turns out this patch/workaround works for me on MPC8536DS.
See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info
Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
According the user manual, we need loop-check the L2 enable bit set.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
nand_boot.c: In function 'board_init_f':
nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
These files were autogenerated by EPSON configuration tools.
This patch replaces the autogenerated file headers by the GPL
license notice.
This change is done with the explicit permission
of Epson Research & Development / IC Software Development.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Some of the new spi flash files were missing explicit license lines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Its possible that we end up with a device tree that happens to be a
particular size that after we call fdt_resize() we don't have any
space left for the initrd mem_rsv.
Fix this be adding a second mem_rsv into the size calculation. We
had one to cover the fdt itself and we have the potential of adding
a second for the initrd.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Move the test up in the function to not hang on systems without ethernet.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
fix the following compile warnings
warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
U-boot for Marvell Kirkwood boards no longer work after the EABI changes
introduced in commit f772acf8a5. This
turns out to be caused by a stack alignment issue. The armv5te
instructions ldrd/strd instructions require 8-byte alignment to work
properly (otherwise undefined behavior).
Tested on an OpenRD base board, where both printouts and ubifs stuff now
works.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430
Highlights of this platform are:
Flash Memory devices:
Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
3 UARTs and expanded 4 UART ports + IrDA
Ethernet, USB
Other peripherals:
TWL5030 PMIC+Audio+Keypad
VGA display
Expansion ports:
Memory devices plugin boards (PISMO)
Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.
Support default jumpering and:
- UART1/ttyS0 console(legacy sdp3430 u-boot)
- UART3/ttyS2 console (matching other boards,
and SDP HW docs)
- Ethernet
- mmc0
- NOR boot
Currently the UART1 is enabled by default. for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.
Conflicts:
Makefile
Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.
Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.
The long term solution(after 2009.11) to this is to
have SOC specific header files.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
We get a compliation warning when we enable the NAND driver
for DM355 leopard. The waring we get is that we have
an implicit declaration of davinci_nand_init.
It is fixed by including the asm/arch/nand_defs.h header file
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
gpmc_config should not be a variant as it is board specific
hence make it a const parameter
Fixes issues identified by Dirk:
- build issue for zoom2
- warnings for all other OMAP3 platforms using nand/onenand etc
Signed-off-by: Nishanth Menon <nm@ti.com>
This patch removes the Sequoia "bootstrap" command and replaces it
with the now common command "chip_config".
Please note that the patches with the dynamic PCI sync clock
configuration have to be applied, before this one should go in.
This is because Sequoia has 2 different bootstrap EEPROMs, and
the old bootstrap command configured different values depending
on the detected PCI async clock (33 vs. 66MHz). With the PCI sync
clock patches, this is not necessary anymore. The PCI sync clock
will be configured correctly on-the-fly now.
Signed-off-by: Stefan Roese <sr@denx.de>
Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:
AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.
Signed-off-by: Stefan Roese <sr@denx.de>
