Commit graph

19 commits

Author SHA1 Message Date
York Sun
4e57382faa powerpc/mpc8xxx: Add DDR2 to unified DDR driver
DDR2 has different ODT table and values. Adding table according to Samsung
application note.

Fix additive latency calculation to avoid interger underflow.

Also converted typedef dynamic_odt_t to struct dynamic_odt.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
cae7c1b56b powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
23f9670f1a powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.

Signed-off-by: York Sun <yorksun@freescale.com>
2011-07-11 13:24:20 -05:00
York Sun
51d498f175 powerpc/mpc8xxx: Add 16-bit support for DDR3
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
Zhao Chenhui
c1fc2d4fc2 powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Poonam Aggrwal
0b3b1766b7 fsl_ddr: Adds 16 bit DDR Data width option
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
f0f899432e powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>
Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
York Sun
91671913f7 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:13 -06:00
York Sun
6b06d7dc07 corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
fa8d23c0ee mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
e1fd16b6f5 mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
York Sun
d2a9568c57 mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Kumar Gala
3dbd5d7d7e powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code
Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Becky Bruce
38dba0c2ff mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts.  Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others.  I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document.  It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled.  This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
York Sun
28a966715b Adding fixed sdram setting for cornet_ds board
800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram
setting. SPD based parameters and fixed parameters can be toggled by hwconfig.
To use fixed parameters,

hwconfig=fsl_ddr:sdram=fixed

To use SPD parameters,

hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20 02:38:39 -05:00
york
7fd101c97b powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
york
5800e7ab32 powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
Dave Liu
f8d05e5e58 fsl-ddr: add the macro for Rtt_Nom definition
add the macro definition for Rtt_Nom termination value for DDR3

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Stefan Roese
a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
Renamed from arch/ppc/include/asm/fsl_ddr_sdram.h (Browse further)