The designware spi driver unconditionally uses polling.
The comment to spi_hw_init() also states that the function should disable
interrupts.
According to the DesignWare DW_apb_ssi Databook, value 0xff in IMR enables
all interrupts. Since we want to mask all interrupts write 0x0 instead.
On the canaan k210 board, pressing the reset button twice to reset the
board will run u-boot. If u-boot boots Linux without having SPI interrupts
masked, Linux will hang as soon as interrupts are enabled, because of an
interrupt storm.
Properly masking the SPI interrupts in u-boot allows us to successfully
boot Linux, even after resetting the board.
Fixes: 5bef6fd79f ("spi: Add designware master SPI DM driver used on SoCFPGA")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
[Niklas: rewrite commit message]
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented
to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects.
However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an
RX FIFO overrun error occurs. Avoid this problem by force setting
fifo_len to 31.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The driver is currently using sizeof(op->cmd.opcode) in the op_len
calculation. Commit d15de62301 ("spi: spi-mem: allow specifying a
command's extension") changed op->cmd.opcode from one byte to two.
Instead, a new struct member op->cmd.nbytes is supposed to be used.
For regular commands op->cmd.nbytes will be one.
Commit d15de62301 ("spi: spi-mem: allow specifying a command's
extension") did update some drivers that overload the generic mem_ops()
implementation, but forgot to update dw_spi_mem_ops().
Calculating op_len incorrectly causes dw_spi_mem_ops() to misbehave, since
op_len is used to determine how many bytes that should be read/written.
On the canaan k210 board, this causes the probe of the SPI flash to fail.
Fix the op_len calculation in dw_spi_mem_ops(). Doing so results in
working SPI flash on the canaan k210 board.
Fixes: d15de62301 ("spi: spi-mem: allow specifying a command's extension")
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
In the TI am65 device tree files there is no reset defined. Also
the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..)
to get the reset.
Lets do the same as the kernel does and make thr reset optinal.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a driver for the SPI controller integrated on Apple SoCs.
This is necessary to support the keyboard on Apple Silicon laopts
since their keyboard uses an Apple-specific HID over SPI protocol.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
Spi memory operation interface is added to zynq qspi
driver to provide an high-level interface to execute
qspi controller specific memory operations by avoiding
spi_mem_exec_op() from spi-mem framework.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220131052240.23403-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a check afer baudrate calculation to see if the resultant value
falls within the range, else set it to default baudrate value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220131052240.23403-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Read only one byte at a time from txbuf as txbuf may not be
aligned and accessing more than a byte at a time may cause
alignment issues. This fixes the issue of data abort exception
while writing to flash device.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220131052240.23403-3-ashok.reddy.soma@xilinx.com
This patch typecasts and accesses rx buf properly as
an unaligned rxbuf, typecasting with u16 and accessing
it causes data abort exception and this patch fixes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220131052240.23403-2-ashok.reddy.soma@xilinx.com
The driver for SPI0 on Allwinner H6 SoCs did not use the correct define
SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner
SoC series.
Fix the conditionals to use the correct define for H6 SoCs. This matches
the conditional logic in the SPL spi driver.
Tested by probing the spi-flash on a pine64_h64-model-b board with
adapted device-tree (disable mmc2, enable spi0).
Signed-off-by: Daniel Wagenknecht <dwagenk@mailbox.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.
The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).
Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmHYV8MACgkQd9zb2sjI
SdELkA/+LjyjJB1KI6/KLLg43zyFeeZX/SjQd5BUIx6EfaCgyTkuq2lzQnErGmbi
HoyMoNLpBxLIL27/5TXPzmKYAeOfKPxA/sXTTtx/l7PG8ncSZIoU0+utqjycdUsK
tSi7EdFzk7/kDDRkqqA7q9nxsPn/7GQNh/ZC9zstMXKaTO/TEb/sZWCMcvQ0MNoB
ynZKOCg5t60UkIYIRwZwC/OS/ssn86dovv/Aa/8D6qpL2AbS5DoCXHuAr8Dnz7fJ
q4rV7oLh7a+WHe/qC7R6ylYFIVVqY5JaIgbLDwuvk1z9o7txchMMQnGgllZ35sN9
LECD2iSDGjhPaHuGCvQwl3TWtIpvtdcP4sQTyJhsXNPxCG6HHvRz7xY4erUohR1I
LIddwCCHeCrBiaamXNbCzph2+JhfPSQ5ETCL9M6iBMxNUPunlCxjfjDzlT/pg11p
EO9PIPjRMR9QhxKtd3gZpyAqPuMBEmIwhDtHI6dL3DNOOsF44ObE4swnzS6qXIDn
jRZzFCC2f/Vyg11YnzFtV3A5eWwJahGDWAGAnnlg6Y8GCLlLmDJitcgA/rWSALko
T5fC8L8IFUx2RnHczyitJ/wqJl9FqOAnIaoB3Trpwp8gFQ15dQjbvoXldQnAjSS2
9bns3zOrx79EF4lbHhwNE9UDLm6OjK5vR3h4bGJvyZBmasVsA90=
=dLEg
-----END PGP SIGNATURE-----
Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmG8PNIcHGV1Z2VuLmhy
aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyN4NCACbdi5EFjoNkGhCWLIX
SobXNcBGaL9Zpr5qZq77uFqFeFPeiAClk9X+TcSHhBTSWPugzNCdXEdENEGdiiOR
Yxe/QvBL7ZsKkhGBw5W8sb81NBPlpnVY7DWufjYvWq7S3C3bIDahQpCeWHKXDO0H
ZzIX1413kfHRKsAIT+IbufmC1dcWY8SWQEArSkL2KhTQyHnLVGAaholgEGXoKMoC
0ACXO+uhqaAY0/1eWvvYjcfotlz881ROajSRITh+Gu0UuHyRr2Fvj7jZvF5E4Q4f
Cu8iciDsimYSDGLZsOJjPIDTfsx9jbA8IcYIAMxOLW8OYbIL6QAUKsJ2LLKao1q5
SYXP
=YXsB
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2022.04 cycle:
This feature set includes : support for the new QSPI hardware on
sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands
and PIO controller on sam9x60/sam9x60ek.
sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
90 MHz DDR/133 MHz SDR
The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
It was wrongly set to "MR", fix it.
Fixes: 52e2565bfb ("spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYZPDrwAKCRDKSWXLKUoM
IS9GAJ93T/uprhLcKWMb+284YMb2caWgOACfZ02nTlzvZKNNXVretJgZaHXqj1M=
=cwTL
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.01-rc3
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
The official devicetree bindings specifies spi-num-chipselects as the
name. Use it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Add the missing compatible to the driver and update the device tree.
We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness
is determined by the little-endian property and not by the compatible
string itself. Further, we won't need and specific details on the DMA
configuration (which is different on the LS1021A). If it's ever needed,
we can later add the more specific "fsl,ls1028a-dspi" compatible to the
driver.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
With current implementation we are seeing write issues at low frequencies
below 15Mhz. Make below changes to fix the issue.
1. Remove dummy genfifo entry in zynqmp_qspi_chipselect() which was
incorrectly added in the past
2. Enable and poll for TX_FIFO_Empty after Tx data is filled in FIFO in
zynqmp_qspi_fill_tx_fifo().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1634652780-21755-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Errata ERR050568 description says that "Flash access by FlexSPI AHB
command may not work with platform frequency equal to 300 MHz" on
LS1028A.
By default, smaller length reads(equal to RX FIFO size) are done by IP
bus and larger length reads using AHB bus. For adding errata workaround,
use IP bus to read entire flash contents and disable AHB path when
platform frequency is 300Mhz.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for disabling AHB bus and read entire flash contents via IP
bus only. Please note, this enables IP bus read using a quirk which can
be enabled directly in device-type data or in existence of an errata
where AHB bus may need to be disabled.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Using read_poll logic.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Set clock related processing into set_speed logic. And Optimize
printing format.
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Disable bi_boot_params for STM32 MCU and MPU boards
- Update stm32-usbphyc node management
- Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
- Convert some USB config flags to Kconfig for various boards
- Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
- Remove specific CONFIG_STV0991 flags
- Remove unused CONFIG_USER_LOWLEVEL_INIT flag
- Add ofdata_to_platdata() callback for stm32_spi driver
- Update for stm32f7_i2c driver
- Remove gpio_hog_probe_all() from STM32 MP1 board
- Fix bind command
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmFlgsIcHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/plnND/4q9HSlvddybIPjBHlW
rXz1ISwj8JZPp7R4MJcB4RiHofYZzjTXx3dDYUif6oQMpCDp64KPfcUDW0kaq8U7
ZFwJvt59boV1XWlonIXMb3gAkY6gFa5PnYAE/YXEqKvPPvUb7FkT7BWxm4LxCGsj
mEmboR8u87s6e4ZP03HJsSVa5FnNwJUZU8b+58Vxp10YC0PPf7kpmgCucDhrghvY
TORlk259KUFoZXz4J4My0VzDdxE05gDqq1m6Xw1CzqcUbGysMvjNEHlxGdYbWD/U
maamP19DUmKUREmpj3kO/JZvacLJlQP/mdGJ0OWKNbIr/3ha4dYagxDoRodEVo0m
DYaaVPGvG24G78d5meB2q9wT0aGdTyaqm+XRBQMvMN2LlaGmu9duA1t6yBuyMcFk
BeA7d0eHMo1ezD9FFZMxwIOAWhJlcYQEAMFhUwkR1B322w0NU4nbl9KRCGuGV2Zp
ZFQV4BoMvb0NwAdo66xwZ+gSq4Wp1y46VM6x2Mw52v2F4p3teeAqR906TdQVYO8+
hlYChO9+qK4JO7LPX/5wQ4FIzcq1HnTzTpuOSf28hsemiPMu0OkAQv1J7DohNZix
wELBA+ZIjGXksmDTPjpXg5CSvVALa/l2G816hp7/XTJ1XRBSz/pzjhp5rwm42zmw
x7EPnwzpAlQCSqTQ0sgO+fgoRA==
=S4kl
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20211012' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Disable ATAGS for STM32 MCU and MPU boards
- Disable bi_boot_params for STM32 MCU and MPU boards
- Update stm32-usbphyc node management
- Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
- Convert some USB config flags to Kconfig for various boards
- Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
- Remove specific CONFIG_STV0991 flags
- Remove unused CONFIG_USER_LOWLEVEL_INIT flag
- Add ofdata_to_platdata() callback for stm32_spi driver
- Update for stm32f7_i2c driver
- Remove gpio_hog_probe_all() from STM32 MP1 board
- Fix bind command
Signed-off-by: Tom Rini <trini@konsulko.com>
This clarifies which callers must be updated to complete the DM_GPIO
conversion.
The only remaining caller of name_to_gpio in generic code is inside the
!DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so
that code cannot be reached. And after this commit, there are only two
remaining implementations of name_to_gpio.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Both dummy.nbytes and dummy.buswidth may be zero. By not checking
the later, it is possible to trigger division by zero and a crash.
This does happen with tiny SPI NOR framework in SPL. Fix this by
adding the check and returning zero dummy bytes in such a case.
Fixes: 38b0852b0e ("spi: cadence-qspi: Add support for octal DTR flashes")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
[trini: Drop Pratyush's RB as his requested changes weren't made as
Marek disagreed]
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last ARCH_MX25 platform, remove those
references as well.
Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last mx35 platform, remove that support as
well.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This is actually a misnomer now, since the phandle info may contain
a driver_info index or a udevice index. Rename it to use the word
'phandle', which seems more accurate. Add a comment while we are here.
Also add a test for this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.
Signed-off-by: Simon Glass <sjg@chromium.org>
DMA is aligned to ARCH_DMA_MINALIGN(64 bytes), but as per spec, alignment
required is 4bytes only. Change DMA alignment from ARCH_DMA_MINALIGN to
GQSPI_DMA_ALIGN. Remove alignment of data length in non-exponential case.
Some minor improvements in the initialization to initialize gen_fifo
threshold and disable qspi controller while setting config register.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Current implementation uses auto mode for starting generic FIFO.
The recommendation from IP designers is to use manual mode, hence
change to manual start mode.
In fill genfifo first write to genfio and then trigger manual start.
Also enable and check for genfifo empty interrupt status in place of
genfifo not full interrupt.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The value CONFIG_ALTERA_SPI_IDLE_VAL is never re-defined by a board.
Rename this to ALTERA_SPI_IDLE_VAL.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Import linux commit 007773e16a6f ("spi: nxp-fspi: Ensure width is
respected in spi-mem operations") to fix SPI access on boards which
don't have all SPI I/O lines connected to the flash.
Since commit 71025f013c ("mtd: spi-nor-core: Rework hwcaps selection")
u-boot figures out the capabilities by looking at spi_mem_supports_op().
The FlexSPI driver doesn't take the board layout into account. Fix that.
Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
