Commit graph

30 commits

Author SHA1 Message Date
Simon Glass
8c103c33fb dm: dts: Convert driver model tags to use new schema
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14 09:43:26 -07:00
Vaishnav Achath
30426492d3 arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash node
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Keerthy
da6a8d9c28 arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max voltages of VDD_CPU
Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU
minimum voltage is .6V & maximum voltage is .9V.

Correct the same. While at it fix the comment to reflect VDD_CPU
instead of VDD_MPU.

Data Sheet Link: https://www.ti.com/lit/gpn/dra829v

Signed-off-by: Keerthy <j-keerthy@ti.com>
2022-02-21 08:35:40 -05:00
Sinthu Raja
1157f36724 arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C
Board ID I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for wakup_i2c0 on which
board ID EEPROM is connected.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Aswath Govindraju
a94d70ad37 arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:04 -05:00
Aswath Govindraju
3c1d89ff76 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:03 -05:00
Aswath Govindraju
fa7a14576d arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10 20:10:20 -04:00
Suman Anna
24f3fb6547 arm: dts: k3-j721e-r5: Remove MAIN R5FSS0 cluster from SPL
The MAIN R5FSS0 cluster and corresponding nodes are no longer required
to be enabled in R5 SPL after removing the support for booting any core
from this cluster on R5 SPL. So, remove these from the relevant dts
files.

This is essentially a revert of the additions done in commit 2984b82b3b
("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL").

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Vignesh Raghavendra
00d6fc9c71 ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Add DM firmware node which will provide DM services during R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Lokesh Vutla
70e167495a arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot.
HBMC nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid any regressions, hbmc nodes are kept
intact. These will be added in kernel in future.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-02-04 20:37:57 +05:30
Nishanth Menon
965db9fb0c arm: dts: k3-*-r5-*-board: Add GTC clock
Add GTC Clock definition as index 0 clock so that we can use the clock
node in the driver later on.

Signed-off-by: Nishanth Menon <nm@ti.com>
2021-01-12 10:59:04 +05:30
Praneeth Bajjuri
9c789fec10 arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 4266MTs DDR configuration.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2021-01-12 10:21:41 +05:30
Vignesh Raghavendra
aaf55800a3 arm: dts: k3-j721e: Increase OSPI default frequency to 50MHz
In 1 bit mode OSPI can work at upto 50MHz, this provides better write
performance. Therefore increase frequency from 40MHz to 50MHz

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-14 15:44:48 +05:30
Tom Rini
2738f0edea Merge tag 'ti-v2020.07-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
K3 J721E:
* OSPI boot support
* Support for loading remote cores in R5 SPL
* PMIC ESM Support
* Minor fixes for R5F and C7x remoteproc drivers

K3 AM654:
* Update AVS class 0 voltages.
* Add I2C nodes

DRA7xx/AM57xx:
* Fixed Android boot on AM57xx

AM33/AM43/Davinci:
* switch to driver model for the net and mdio driver for baltos
* Add DM/DTS support for omap video driver
* Enable fastboot on am335x-evm
2020-03-17 11:59:58 -04:00
Faiz Abbas
0abf600746 arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocks
Update the dummy clock names to use unique identifiers. Otherwise the
previous node just gets overwitten by the next one with the same name.
This fixes eMMC boot not working on J721e-evm.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09 08:33:16 +08:00
Keerthy
6d310ba50c arm: dts: k3-j721e-r5-common-proc-board: Add ospi1 flash node
Add ospi1 flash node required for QSPI boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06 12:53:00 +05:30
Keerthy
896cf0e20a arm: dts: k3-j721e: Enable ospi1/qspi
Enable the ospi1/qspi for both r5 and a72 configurations.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06 12:53:00 +05:30
Tero Kristo
7304546071 arm: dts: k3-k721e: Add Main domain ESM support
Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Keerthy
2984b82b3b arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL
Enable MAIN domain r5fss0 cluster and its core0 in R5 spl.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-03-03 13:08:14 +05:30
Vignesh Raghavendra
224d7fe263 ARM: dts: k3-j721e: Add OSPI DT nodes
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support
OSPI boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-03 13:08:13 +05:30
Lokesh Vutla
fde109dc75 arm: dts: k3-j721e-r5-common-proc-board: Disable power-domains for mcu uart
mcu uart will be used during uart boot for loading sysfw.itb. Since
sysfw is not yet available during uart load, power-domain cannot be
enabled. We need to rely on ROM for doing that, so disable power-domains
and clocks for mcu uart. Also fix the mcu uart frequency.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-13 21:39:17 +05:30
Vignesh Raghavendra
b6427783a8 arm: dts: k3-j721e-common-proc-board: Enable I2C expander for SPL
IO expanders are required to power cycle SD card. So enable the same

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
b070f58b44 arm: dts: k3-j721e-common-proc-board: Enable USB0 in peripheral mode
Enable USB0 in peripheral mode so that it be used for DFU

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Faiz Abbas
ccc855e9d9 arm: dts: k3-j721e-common-proc-board: Add pinmux for SD card
Add pinmux for sdhci1 node connected to the SD card.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
5aeab3bf5e arm: dts: k3-j721e: Add DT nodes for USB
J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Keerthy
2f71498d52 arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supply
Hook buck12_reg to vtm avs supply

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
0f63ceaf54 arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 node
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
69eceae870 arm: dts: k3-j721e-r5-common-proc-board: Add VTM node
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Lokesh Vutla
ec2fa9f76e arm: dts: k3-j721e: Add ddr node
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2019-10-25 17:33:21 -04:00
Lokesh Vutla
aebb2a499e arm: dts: k3-j721e: Add r5 specific dt support
Add initial support for dt that runs on r5.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:29 -04:00