Commit graph

7 commits

Author SHA1 Message Date
Roger Quadros
ffefc72083 arm: dts: k3-am64: sync with Linux DT files
Sync AM64 DT files with Linux v6.2-rc4

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-02-06 13:04:53 -05:00
Christian Gmeiner
dcbc95c23c arm: dts: ti: k3-am64-main: Add RTI watchdog nodes
Add the needed bus mappings for the two main RTI memory ranges and
the required device tree nodes in the main domain.

Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-11-02 13:58:17 -04:00
Hari Nagalla
3d64cffa91 arm: dts: k3-am64: Add support for ESM device nodes
Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM
nodes to the AM64 device tree.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04 19:02:04 -04:00
Tom Rini
fa09b12dc5 arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14
This resyncs the dts files for all of the currently in-tree K3
platforms, along with relevant bindings, with the v5.14 Linux Kernel
release.  Of note are that the main-navss/mcu-navss nodes were renamed
to main_navss / mcu_navss and so the u-boot.dtsi files needed to be
updated to match.

Tested on j721e_evm and am65x_evm.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-03 11:59:22 -04:00
Vignesh Raghavendra
bc17fccbd0 ARM: dts: k3-am64-main: Add CPSW DT nodes
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Lokesh Vutla
45b7a9fc08 arm: dts: am642-evm: Add I2C nodes
Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Dave Gerlach
58211db0a8 arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30