3 commits

Author	SHA1	Message	Date
Pragnesh Patel	bc8d12bfd8	riscv: timer: Add support for an early timer ... Added support for timer_early_get_count() and timer_early_get_rate() This is mostly useful in tracing. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>	2021-01-18 11:06:32 +08:00
Simon Glass	0fd3d91152	dm: Use access methods for dev/uclass private data ... Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>	2021-01-05 12:24:40 -07:00
Sean Anderson	47d7e3b5eb	riscv: Move timer portions of SiFive CLINT to drivers/timer ... Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>	2020-10-26 10:01:28 +08:00