Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.
Signed-off-by: Simon Glass <sjg@chromium.org>
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.
This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun <yorksun@freescale.com>
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun <yorksun@freescale.com>
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.
For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."
This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
This allows the USB code to determine whether a USB bus reset was issued,
which in turn allows the code to differentiate between a detach (return
to shell prompt) and a board reset/reboot request.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
New dfu_usb_get_reset() method is necessary to distinct two different
use cases of dfu-util program.
This method checks if the USB bus reset has been really performed after
DFU DETACH.
Without this function the previous DFU behavior is preserved.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
This commit provides distinction between DFU device detach and reset.
The -R behavior is preserved with proper handling of the dfu-util's -e
switch, which detach the DFU device.
By running dfu-util -e; one can force device to finish the execution of
dfu command on target and execute some other scripted commands.
Moreover, some naming has been changed - the dfu_reset() method now is known
as dfu_detach(). New name better reflects the purpose of the code.
It was also necessary to increase the number of usb_gadget_handle_interrupts()
calls since we also must wait for detection of the USB reset event.
Example usage:
1. -e (detach) switch
dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e
access to u-boot prompt.
2. -R (reset) switch
dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage
target board reset
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
The nios2-yanu.h contains hardware registers and bits of
opencores yanu. As there is no other user of this header
, it should be moved into the driver.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
CC: Renato Andreola <renato.andreola@imagos.it>
The nios2-io.h defines hardware registers and bits of several FPGA
IP cores. It could be divided in to the specific drivers, including
altera timer, altera sysid, altera uart and altera jtag uart. The
altera pio and altera spi drivers use their own hardware definitions.
The removal of nios2-io.h will help modularity and maintenance.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <pavel@denx.de>
We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected
to the CPSW MAC) that the network performance in U-Boot is quite poor. Only
when the transfer is started without a cable connected, and the cable is
plugged after the first timeout "T" occured, an increased in performance
can be seen. Debugging has revealed, that the cpsw driver has constant
link checking builtin into the rx and tx functions. This results in the
bad performance and seems to be unnecessary. The link has already been
checked in the init function, before the transfer is started. This usually
is sufficient.
BTW: I have seen no other network driver in U-Boot so far, that constantly
checks for link in the rx / tx functions.
The performance numbers on the DXR2 board are:
0.56 MiB/s cpsw_check_link() in rx and tx path
0.87 MiB/s cpsw_check_link() only in tx path
1.0 MiB/s cpsw_check_link() only in rx path
2.7 MiB/s no cpsw_check_link() in rx and tx path
So with this patch the network performance on DXR2 increases from 0.56
to 2.7 MiB/s (nearly 5 times as fast).
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Samuel Egli <samuel.egli@siemens.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
snyc with linux v3.15:
commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Jun 8 11:19:54 2014 -0700
Linux 3.15
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:
- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
resync ubi subsystem with linux:
commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Mar 30 20:40:15 2014 -0700
Linux 3.14
A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
- move linux specific defines from usb and video code
into linux/compat.h
- move common linux specific defines from include/ubi_uboot.h
to linux/compat.h
- add for new mtd/ubi/ubifs sync new needed linux specific
defines to linux/compat.h
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[trini: Add spin_lock_irqsave/spin_unlock_irqrestore dummies from
usb/lin_gadet_compat.h]
Signed-off-by: Tom Rini <trini@ti.com>
Implement proper support for cache flushing and invalidation into the
Intel e1000 NIC driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.
Tom suggested to remove this board.
Remove also omap1510_udc.c because this is the last board
to enable it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
The following configs are not defined at all:
- CONFIG_INCA_IP_SWITCH
- CONFIG_PBL2800_ETHER
- CONFIG_PHY_ICPLUS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.
For copper cable, set below env in hwconfig:
fsl_10gkr_copper:<10g_mac_name>
the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.
For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:
fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2
For fiber cable:
1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.
When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.
Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This Patch updates error print for QE which should be easily understood
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.
Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).
To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Since rgb2ycbcr_coeff and friends are declared const, but assigned
to a void pointer, clang will warn that the const is implicity casted
away. If the pointer is changed to void const * gcc will warn when it
is implicitly casted to a const int array. Just add a correctly
typed pointer instead to prevent these casts and hence the warnings.
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows. In this way, we align the implement
to the freescale internal IPUv3 driver. After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
common/lcd.c)
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
The following configs are not defined at all.
- CONFIG_OMAP1510
- CONFIG_OMAP_1510P1
- CONFIG_OMAP_SX1
- CONFIG_OMAP3_DMA
- CONFIG_OMAP3_ZOOM2
- CONFIG_OMAP_INNOVATOR
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
R8A7780 and R7A7791 of rmobile supports External Clock mode, and these uses
different from Internal Clock mode registers and calculations to the baud rate
setting. This adds function for External Clock mode.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
R8A7794 has DL and CKS register, and these registers are used in external clock
mode. This adds support these for R8A7794.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
echi-rmobile does not support xHCI. This removes xHCI address
from address table. And this revise a value of CONFIG_USB_MAX_CONTROLLER_COUNT
for lager board and koelsh board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
R8A7794 has same IP of USB controller as R8A7790 and R8A7791.
This addes support for R8A7794.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The buffer is too small if it's < size to read, not if it's <= the size.
This fixes the 1MB test case on Tegra, which has a 1MB buffer.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This allows the backend to free any resources allocated during the
relevant dfu_fill_entity_*() call. This will soon be used by the
SF backend.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
CONFIG_SYS_DFU_DATA_BUF_SIZE may be large to allow for FAT/ext layouts
to transfer large files. However, this means that individual write
operations will take a long time. Allow backends to specify a maximum
buffer size, so that each write operation is limited to a smaller data
block. This prevents the DFU protocol from timing out when e.g. writing
to SPI flash. I would guess that NAND might benefit from setting this
value too, but I can't test that.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Devices are not all identified by a single integer. To support
this, defer the parsing of the device string to the IO backed, so that
it can apply the appropriate rules.
SPI devices are specified as controller:chip_select. SPI/SF support will
be added soon.
MMC devices can also be specified as controller[.hwpart][:partition] in
many commands, although we don't support that syntax in DFU.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Fix calls to dfu_write() and dfu_flush() to detect errors in the I/O
itself. This could happen due to problems with the storage medium, or
simply when trying to write a FAT/ext file that is larger than the buffer
dfu_mmc.c maintains for this purpose.
Signal the error by switching the DFU state/status. This will be picked
up by the DFU client when it sends the next DFU request. Note that errors
can't simply be returned from e.g. dnload_request_complete(), since that
function has no way to pass errors back to the DFU client; a call to
dnload_request_complete() simply means that a USB OUT completed.
This error state/status needs to be cleared when the next DFU client
connects. While there is a DFU_CLRSTATUS request, no DFU client seems to
send this. Hence, clear this when selecting the USB alternate setting on
the USB interface.
Finally, dfu.c relies on a call to dfu_flush() to clear up the internal
state of the write transaction. Now that errors in dfu_write() are
detected, dfu_flush() may no longer be called for every transaction.
Separate out the cleanup code into a new function, and call it whenever
dfu_write() fails, as well as from any call to dfu_flush().
Signed-off-by: Stephen Warren <swarren@nvidia.com>
DFU read support appears to rely upon dfu->read_medium() updating the
passed-by-reference len parameter to indicate the remaining size
available for reading.
dfu_read_medium_mmc() never does this, and the implementation of
dfu_read_medium_nand() will only work if called just once; it hard-codes
the value to the total size of the NAND device irrespective of read
offset.
I believe that overloading dfu->read_medium() is confusing. As such,
this patch introduces a new function dfu->get_medium_size() which can
be used to explicitly find out the medium size, and nothing else.
dfu_read() is modified to use this function to set the initial value for
dfu->r_left, rather than attempting to use the side-effects of
dfu->read_medium() for this purpose.
Due to this change, dfu_read() must initially set dfu->b_left to 0, since
no data has been read.
dfu_read_buffer_fill() must also be modified not to adjust dfu->r_left
when simply copying data from dfu->i_buf_start to the upload request
buffer. r_left represents the amount of data left to be read from HW.
That value is not affected by the memcpy(), but only by calls to
dfu->read_medium().
After this change, I can read from either a 4MB or 1.5MB chunk of a 4MB
eMMC boot partion with CONFIG_SYS_DFU_DATA_BUF_SIZE==1MB. Without this
change, attempting to do that would result in DFU read returning no data
at all due to r_left never being set.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.
Call it simply 'PFUZE100' instead.
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com
Signed-off-by: Andy Fleming <afleming@gmail.com>
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This parameter should also be supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.
Fix these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The Allwinner aka sunxi SoCs have one or more USB host controllers.
This adds a driver for their EHCI.
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.
The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port. This is added under a
suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
