This commit adds support for 96Boards Dragonboard820C.
The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.
Features
- 4x Kyro CPU (64 bit) up to 2.15GHz
- USB2.0
- USB3.0
- ISP
- Qualcomm Hexagon DSP
- SD 3.0 (UHS-I)
- UFS 2.0
- Qualcomm Adreno 530 GPU
- GPS
- BT 4.2
- Wi-Fi 2.4GHz, 5GHz (802.11ac)
- PCIe 2.0
- MIPI-CSI, MIPI-DSI
- I2S
U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.
For detailed build instructions see readme.txt in the board directory.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Move some of the code for the "lane_bank" and "cpld" code local
commands so that they are not built for SPL as they can only be
used in full U-Boot. This means we can mark a few functions as
static as well now.
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Tested-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add a CONFIG_SPL_BUILD guard around the code for the "mux" command so
it is not included in SPL.
Cc: Qiang Zhao <qiang.zhao@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Qiang Zhao <qiang.zhao@nxp.com>
QMAP value contains information about QSPI chip-selects. These bits
are used to display information of boot device in checkboard()
function.
QMAP value is stored in most significant 3-bits of 8-bit register
brdcfg[0] in Qixis, this patch corrects code to get QMAP bits using
below logic:
(brdcfg[0] >> 5) & 0x7
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove Board Arch print as its value is always constant '1' and does
not contain any important information to display during boot.
Add print to display Board FPGA version.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of chain of trust with confidentiality along with distro
boot, linux kernel image needs to be stored in encrypted form on
ext4 boot partition. So enable CONFIG_CMD_EXT4_WRITE in case of
Secure boot on ARM based platforms.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII
PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Like many other i.MX6 based boards, there are multiple variants of
the cm-fx6 module featuring different SoC variants. Furthermore, the
module can be paired with multiple baseboards.
At the same time modern distribution like Fedora require U-Boot to
select a proper devicetree which depends on the SoC variant and the
baseboard.
Thus, export the SoC variant and the actual board to the environment
following the conventions of other i.MX6 devices (e.g. the NXP boards)
such that the environment can select a devicetree file to load.
For now, we only know for sure that the cm-fx6 module and the SB-fx6m
baseboard amount to a Utilite Computer variant (depending on the SoC).
Further combinations may be added in the future; e.g. CompuLab's
evaluation board once someone can verify the identification string
stored in its eeprom.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently mmdc_do_dqs_calibration() and mmdc_do_write_level_calibration()
show the same error message, which is confusing for debugging.
Disambiguate the mmdc_do_dqs_calibration() error message.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
mx6sabresd board uses the following pins for console:
PAD_CSI0_DAT10__UART1_TX_DATA
PAD_CSI0_DAT11__UART1_RX_DATA
,so put it in the same config option as wandboard.
mx6sabreauto board uses the following pins for console:
PAD_KEY_COL0__UART4_TX_DATA
PAD_KEY_ROW0__UART4_RX_DATA
So do not mention sabreauto board as part of the UART1_SD3_DAT6_7 option.
The config option for sabreauto can be added later when needed.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
The code for programming the OTP fuses on the PMIC PF0100 can only be
used in full U-Boot, so do not build / link it into SPL.
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
The command can only be used from full U-Boot, so do not build it into
SPL.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The command can only be used from full U-Boot, so do not build it into
SPL.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Because kernel set WDOG_B mux before pad with the common pinctrl
framwork now and wdog reset will be triggered once set WDOG_B mux
with default pad setting, we set pad setting here to workaround this.
Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
as GPIO mux firstly here to workaround it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Enable I2C/MMC/GPIO/REGUALTOR/PMIC/USB DM drivers.
There are some dependency, such as when DM MMC enabled, USB compile error.
Also the i.MX I2C MMC DM driver does not support legacy GPIO interface.
So enable them all together.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Add pfuze dm code, this code could be enabled with CONFIG_DM_PMIC_PFUZE100.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Add nx25-ae250 board to do platform initializations.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
The clock selection is done now from the am335x-fb code, so there is no
more need doing this in the board code.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Actual am335x-fb implementation takes now a real clock frequency instead
a divider. So this component doesn't need to know anymore some base
frequency of the LCDC, we simply provide the pixel-clock frequency.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Using changes in this patch we were able to reduce approx 8k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1088a/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1088a/ls1088a.c to keep
board_early_init_f funcations in case of SPL build.
3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
- Create new board/freescale/common/fsl_portals.c to house shared
device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
setup to disable interrupts on all QMan and BMan portals. It is
needed because the interrupts are enabled by default for all portals
including unused/uninitialised portals. When the kernel attempts to
go to deep sleep the unused portals prevent it from doing so
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Given gcc-6.1 and later we can now safely have strings discarded when
the functions are unused. This lets us drop certain cases of not
building something so that we don't have the strings brought in when the
code was discarded. Simplify the code now by dropping guards we don't
need now.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board offers :
_ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
and 324 Kbytes of RAM in BGA216 package
_ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
_ Mbed-enabled (mbed.org)
_ USB functions: USB virtual COM port, mass storage, debug port
_ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
touch screen
_ SAI Audio DAC, with a stereo headphone output jack
_ 3 MEMS microphones
_ MicroSD card connector
_ I2C extension connector
_ 4Mx32bit SDRAM
_ 128-Mbit Quad-SPI NOR Flash
_ Reset and wake-up buttons
_ 4 color user LEDs
_ USB OTG FS with Micro-AB connector
_ Three power supply options:
_ Expansion connectors and Arduino™ UNO V3 connectors
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.
Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.
Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.
Enable also CLK flag.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Remove serial_stm32.c driver and uart init from board file,
use available DM serial_stm32x7.c driver compatible for
STM32F4/F7 and H7 SoCs.
The serial_stm32x7.c driver will be renamed later with a more
generic name as it's shared with all STM32 Socs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM stm32_sdram.c driver instead of board
SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Support for that board got introduced recently without the maintainers
part. Let's fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
and connectors are in the exact same position as on the Raspberry Pi B+.
Raspberry Pi B+ like peripherals supported on this board include:
- Power input through micro-USB connector (without USB OTG)
- Native 100 Mbps ethernet using the internal PHY, as opposed to
USB-based on the RPi
- 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
being connected through a USB 2.0 hub on the RPi
- TV and audio output on a 3.5mm TRRS jack
- HDMI output
- Micro-SD card slot
- Standard RPi B+ GPIO header, with the standard peripherals routed to
the same pins.
* 5V, 3.3V power, and ground
* I2C0 on the H3 is routed to I2C1 pins on the RPi header
* I2C1 on the H3 is routed to I2C0 pins on the RPi header
* UART1 on the H3 is routed to UART0 pins on the RPi header
* SPI0 on the H3 is routed to SPI0 pins on the RPi header,
with GPIO pin PA17 replacing the missing Chip Select 1
* I2S1 on the H3 is routed to PCM pins on the RPi header
- Additional peripherals from the H3 are available on different pins.
These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
In addition, there are a number of new features:
- Console UART header
- Consumer IR receiver
- Camera interface (not compatible with RPi)
- Onboard microphone
- eMMC expansion module port
- Heatsink mounting holes
This patch adds defconfig and dts files for this board. The dts file is
the same as the one submitted for inclusion in Linux, with some minor
revisions to match the dtsi file and old EMAC bindings in U-boot.
Since the OTG controller is wired to a USB host port, and the H3 has
proper USB hosts to handle host mode, the MUSB driver is not enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
board/icorem6_rqs/ is forgot to remove while moving
common board files together in
(sha1: 52aaddd6f4)
"i..MX6: engicam: Add imx6q/imx6ul boards for existing boards"
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
commit 20f1471416 ("imx: spl: Update NAND bootmode detection bit")
broke the NAND bootmode detection by checking if
BOOT_CFG1[7:4] == 0x8 for NAND boot mode.
This commit essentially reverts it, while using the IMX6_BMODE_*
macros that were introduced since.
Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection
is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not
necessarily 0x0 in this case.
Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf,
like it was in the code before.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tim Harvey <tharvey@gateworks.com>
This is a virtual "board" that uses configuration files and
Kconfig to define the memory layout used by a real board during
the board bring-up process.
It generates an SPL image that can be loaded using imx_usb or
SB_LOADER.exe.
When run, it will generate a set of calibration constants for
use in either or both a DCD configuration file for boards that
use u-boot.imx or struct mx6_mmdc_calibration for boards that
boot via SPL.
In essence, it is a configurable, open-source variant of the
Freescale ddr-stress tool.
https://community.nxp.com/docs/DOC-105652
File mx6memcal_defconfig configures the board for use with
mx6sabresd or mx6qsabreauto.
Signed-off-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
We want to have the same configuration defaults for the RK3368-uQ7
as for the RK3399-Q7: this change reduces the default env-size to
8KiB to ensure that it does not overlap the boot-payload on SD/MMC
configurations.
References: commit fe529e6597 ("rockchip: rk3399-puma: reduce env size to 8kiB")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion NOT 'Tomato'
The fix was provided by Khadas Team member 'numbqq'.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit clears 'ethaddr' before calling 'smc911x_initialize' to
allow the SROM MAC address to be assigned properly.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
This commit changes the size of the enviroment (for the RK3399-Q7) to
8kiB for all possible locations of the environment (i.e. even when the
environment is saved to SD card).
With the default of 32kiB, the environment overwrites the SPL
stage which lives at 16kiB.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Reworked commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The DDR DRAM calibration doesn't work on T-topology sometimes, so disable it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Secure boot is not enabled in warp imximage.cfg, add support for it.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Secure boot is not enabled in mx6slevk imximage.cfg, add support for it.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Currently only imx6sx-sdb.dtb is loaded, but if revA board is used the
correct dtb is imx6sx-sdb-reva.dtb, so make this possible.
While at it, remove an extra 'mmc dev'.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
NXP development boards based on i.MX6/i.MX7 contain the board
revision information stored in the fuses.
Introduce a common function that can be shared by different boards and
convert mx6sabreauto to use this new mechanism.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Commit 5248930ebf ("dm: imx: cm_fx6: Enable more driver model support")
enabled driver model support for MMC. Remove the old mmc init code, which
is no longer used, from the board file.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 5248930ebf ("dm: imx: cm_fx6: Enable more driver model support")
enabled driver model support for AHCI. Remove the old, now unused, sata
init code from the board file.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We are going to be using check_time() on more than the mx53ppd, move this
function to a common location.
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Linux device tree contains "ethernet" node for all possible
interface supported by SoC i.e. LS1046A.
It is not necessary for a SerDes protocol to support all possible
interface. So disable unavailable "ethernet" node in device tree.
Also, enable FDT_SEQ_MACADDR_FROM_ENV to fetch MAC address
sequentially from environment variables
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
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Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.01-rc2-v2
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
Since we support ATF in SPL and add script for it, let's make the
document up to date.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Access the timestamp ref ctrl register only if runinng
at el3 level otherwise just return. This change fixes
the issue when CRL APB is marked as secure and accessing
when not in el3 causes exception.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit adds ENV_SIZE and ENV_OFFSET configuration items for
ARCH_ROCKCHIP, but keeps these non-visible (i.e. not prompt is given).
With these new items present, the configuration from the header files
is moved to Kconfig.
Keeping these non-visible is necessary to have the possibility to
select new default values if CONFIG_IS_IN_* is changed (interactively
or with oldconfig). Otherwise it will always be set to a previous
value if used with a prompt. As an example if we do a defconfig with
CONFIG_IS_IN_MMC and change it to CONFIG_IS_IN_SPI_FLASH via
menuconfig, ENV_SIZE and ENV_OFFSET will not be changed to the correct
values as defconfig will already have set them to the default values
of CONFIG_IS_IN_MMC in .config.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The PCIe reset signal is connected to GPIO4_C6 on the Puma
module. This pin is supplied by 1.8V, but the default iodomain
setting is 3.0V and in this situation the pin is unable to go
high.
Linux assumes that this signal works in early boot
as PCIe is probed before loading the iodomain driver.
Make PCIe work in Linux by setting the gpio4cd iodomain to 1.8V.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
I2C reading for DIP switch setting is not reliable for LS1012ARDB
RevD and later versions. This patch is to add hwconfig support to
enable/disable eSDHC1 manually for these boards. Also drop 'status'
fix-up for eSDHC0 and leave it as it is. It shouldn't always be
fixed up with 'okay'.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add LS1012ARDB RevC/RevC1/RevC2/RevD/RevE information and
detect it when u-boot starts up.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch is to clean up definitions for I2C IO expanders.
The value 0x10 of __SW_BOOT_EMU is wrong. It should be 0x2.
Fixed it in this patch.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Function fdt_fixup_board_enet() performs fdt fixup. Only return
fdt_status_okay() when both MC is applied and DPL is deployed, else
return fdt_status_fail().
This check is added to LS1088A/LS2080A/LS2088A boards.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove silicon prefix. Automotive grade devices are using xazu instead
of xczu prefix.
The patch "fpga: xilinx: Check for substring in device ID validation"
(sha1: f72132673a)
enables this functionality for zynq devices that only substrings are
checked.
Unfortunately there is no way how to detect device grade that's why
this change is reasonable.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup bootmode variable based on bootmode selection.
This is helping with setting up boot method.
Also setup sdbootdevice.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dont read boot mode register directly read it using
zynqmp_mmio_read().
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The BRDCFG5[SPISDHC] register field of Qixis device is used
to control SPI and SDHC signal routing.
10 = Force SDHC Mode
- SPI_CS[0] is routed to CPLD for SDHC_VS use.
- SPI_CS[1] is unused.
- SPI_CS[2:3] are routed to the TDMRiser slot.
11 = Force eMMC Mode
- SPI_CS[0:3] are routed to the eMMC card.
0X = Auto Mode
- If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode
described above.
- Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC
mode described above.
In default the hardware uses auto mode, but sometimes we need
to use force SDHC mode to support SD card hotplug, or SD sleep
waking up in kernel. This patch is to support force SDHC mode
by hwconfig.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Falcon mode was already working with SD card. This enables the
unlocking of NAND to allow the NAND read & write. This also
expands the README file based on the am335x describing how to
setup Falcon mode.
Signed-off-by: Adam Ford <aford173@gmail.com>
The Micron Flash is locked by default. This will automaticlly
unlock so manually unlocking is unnecessary in U-Boot.
Signed-off-by: Adam Ford <aford173@gmail.com>
DW SDIO controller has external CIU clock divider controlled via
register in the SDIO IP. Due to its unexpected default value
(we expected it to divide by 1 but in reality it divides by 8)
SDIO IP uses wrong CIU clock (it should be 100000000Hz but actual
is 12500000Hz) and works unstable (see STAR 9001204800).
So increase SDIO CIU frequency from actual 12500000Hz to 50000000Hz
by switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Add bits to support yet another board, the R8A77995 D3 Draak.
The DT file is from Linux 4.15-rc1 , commit
b35334447513c14a4dd55a67c269a743d4a4824b .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add bits to support yet another board, the R8A77970 V3M Eagle.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Linux preserves leading zeros in /proc/cpuinfo, so we
should as well.
Otherwise we have the situation that
/sys/firmware/devicetree/base/serial-number
and /proc/cpuinfo disagree in Linux.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add the secure boot defconfigs for QSPI boot on LS1088ARDB
and LS1088AQDS platforms.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC
phase using esbc_validate command.
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment
Add header address for PPA to be validated during ESBC phase for
LS1088A platform based on LAyerscape Chasis 3.
Moves sec_init prior to ppa_init as for validation of PPA sec must
be initialised before the PPA is initialised.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IFC-NOR and QSPI-NOR signals are muxed on SoC to save pins
Add fsl_fdt_fixup_flash() to disable IFC-NOR node in dts
if QSPI is enabled and vice-versa
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.
Signed-off-by: York Sun <york.sun@nxp.com>
Odroid HC1 board is based on Odroid XU4 board, but it has no HDMI,
no eMMC, no build-in USB3.0 hub, no extension port pins, and no GPIO
button. USB3.0 ports are used for build-in JMicron USB to SATA bridge
and Gigabit R8152 ethernet chips. HC1 uses only passive cooling.
This patch also updates Odroid's ADCmax array and reduces ADC tolerance
to 1% to ensure that XU4 and HC1 revisions are properly detected.
I've tested this with XU3, XU3-lite, XU4 and HC1 boards. In case of my test
boards I got following values from ADC register: 372, 370, 1281 and 1313.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware
and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was moved
and grown for security reasons.
But mainline U-Boot and Linux has the old address and size fixed.
These SoCs have a register interface to get the two firmware reserved
memory start and sizes.
This patch adds a dynamic reservation of the memory zones in the device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved zones.
Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2].
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html
Changes since v1:
- switched the #if to if(IS_ENABLED()) to compile all code paths
- renamed function to meson_board_add_reserved_memory()
- added a mem.h header with comment
- updated all boards ft_board_setup()
Changes since RFC v2:
- reduced preprocessor load
- kept Odroid-C2 static memory mapping as exception
Changes since RFC v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[trini: Fix warning on khadas-vim over missing <asm/arch/mem.h>
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds platform code for the Khadas VIM board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.
This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.
The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds platform code for the Libre Computer CC "Le Potato" board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.
This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.
The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Switch P212 Ethernet init to the common Ethernet init function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Switch Odroid-C2 Ethernet init to the common Ethernet init function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This header was renamed to rawnand.h in Linux.
The following is the corresponding commit in Linux.
commit d4092d76a4a4e57b65910899948a83cc8646c5a5
Author: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Fri Aug 4 17:29:10 2017 +0200
mtd: nand: Rename nand.h into rawnand.h
We are planning to share more code between different NAND based
devices (SPI NAND, OneNAND and raw NANDs), but before doing that
we need to move the existing include/linux/mtd/nand.h file into
include/linux/mtd/rawnand.h so we can later create a nand.h header
containing all common structure and function prototypes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed. To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset via a GPIO trigger.
This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
board-support and the documentation for the new property
(sysreset-gpio) within the /config-node.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For some versions of the RK3399-Q7 (at least revisions v1.1 and v1.2
are affected), we need to turn on the power for the port connected to
the on-module USB hub only when the device is probed for the first
time to ensure that the hub does not enter a low-power mode (that
U-Boot's USB stack can't deal with).
Note that this is needed for U-Boot only, as Linux eventually manages
to attach the hub even when it has entered into its low-power state
(when the hub wakes up the next time) after a few seconds.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Even if the board-specific directory Makefile doesn't have any
targets, it still needs to exist.
This adds a minimal Makefile for the board/rockchip/evb_rk3128
directory and a evk-rk3128.c (as built-in.o needs to be built
for every directory that a Makefile gets run for).
Fixes: c7a6866 ("rockchip: rk3128: add evb-rk3128 support")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
After commit d962e5dadc2c("rockchip: mkimage: use spl_boot0 for all Rockchip SoCs"),
the mkimage will not pad the Tag memroy, so we shoud
pass a Taged ddr.bin/spl.bin to it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if there were ever a board that did need to set these
explicitly they would run into unexpected issued.
Update the comments to reflect the correct order of structure members.
Reported-by: Tobi Wulff <tobi.wulff@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPL
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
This board is based on the Atmel 9x5 eval board.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPL
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.
Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.
For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Drop the ad-hoc DRAM configuration with macros and just decode
the DRAM configuration from device tree instead. This makes it
far cleaner and easier.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since checkboard() is gone, rmobile_sysinfo is also pointless on Gen3.
Furthermore, nuke ad-hoc CONFIG_RCAR_BOARD_STRING which is also dead.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
We can now use rmobile_get_cpu_type() to check the CPU ID rather
than using a macro, make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since the Gen3 clock driver now has a .remove callback, it is no
longer necessary to shut the clock down before booting Linux in the
arch_preboot_os hook. Stop using it and while doing so, remove all
the ad-hoc config options which this hook used.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
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Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.
The patch is also marking ps7_config as weak function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
The lowlevel_display() function includes a "1:" label which is never
used. Remove it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.
Remove the redundant assignment to v0.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.
These efuse bits are setup for certain devices.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.
ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000
was hardcoded.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.
Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Michal Simek <monstr@monstr.eu>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
icorem6 has sd on usdhci1 which is devno 0 so return proper
devno from board_mmc_get_env_dev for icorem6 and icorem_6rqs
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
As per USDHC boot eFUSE descriptions:
USDHC3 => devno 2
USDHC4 => devno 3
Linux will detect mmc0, mmc1, mmc2 based on the status
"okay" on usdhc so imx6qdl-icore-rqs.dtsi has enabled
usdhc1, usdhc3 and usdhc4.But U-Boot can detect based
on the aliases so add mmc1, mmc2 for usdhc3 and usdhc4
respectively and return the board_mmc_get_env_dev
by subtracting -1
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
When usb_hub_reset_devices is called, it should be passed both an
indicator which hub it should operate on and what port number (local
to that hub) should be reset.
Previously, the usb_hub.c code did not include such context and
always started resets from port number 1, performing multiple
reset-requests for the same devices:
/*
* Reset any devices that may be in a bad state when applying
* the power. This is a __weak function. Resetting of the devices
* should occur in the board file of the device.
*/
for (i = 0; i < dev->maxchild; i++)
usb_hub_reset_devices(i + 1);
This adds an additional 'hub' parameter to usb_hub_reset_devices
that provides the context to fully qualify the port-number in.
Existing implementations are changed to accept and ignore the new
parameter.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
For the RK3368-uQ7, we can now update the .its file to mark the
Trusted Firmware as out 'firmware' bootable and annotate both ATF and
U-Boot with an OS-type.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit updates the .its file for the RK3399-Q7 to use the new
features and demonstrates how to use those:
* it marks the ATF as the 'firmware'
* it tracks the OS-type for U-Boot and ATF
* it loads the PMU (M0) firmware to DRAM and records the location
to /fit-images (where our ATF reads it from)
With the handoff of the next-stage FDT to ATF in place, we can now use
this to pass information about the load addresses and names of each
loadables to ATF: now we can load the M0 firmware into DRAM and avoid
overwriting parts of the SPL stage. This is achieved by changing our
.its-file to use an available area of DRAM as the load-address.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Create board support for GE PPD, based on mx53loco.
Use mx53ppd_defconfig make target to configure for this board.
Signed-off-by: Peter Senna Tschudin <peter.senna@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The VPD data is used on a number of GE products. Move the parsing code to
a common location so that we can share this code.
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Acked-by: Stefano Babic <sbabic@denx.de>
This reverts commit b8b9790e23.
Some wandboard variants no longer boot after this commit, so keep
the original delay to avoid the boot regression.
Reported-by: Varga Zsolt <vazso@vazso.hu>
Tested-by: Varga Zsolt <vazso@vazso.hu>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Update arm_pl180_mmci_init() prototype by adding struct mmc**
param. This is needed before converting this driver to driver model
in order to use arm_pl180_mmci_init() in driver model and in none
driver model implementation
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch adds support for the Internal RMII Ethernet PHY on the
Amlogic P212 Reference Board.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds platform code for the Amlogic P212 reference board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.
This initial submission only supports UART and MMC/SDCard, support for the
internal Ethernet PHY in Work In Progress.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
All regulators are hooked to EN_Pin at reset so that EN Pin controls
their state. Hook the LDO1 regulator to EN pin which at reset is not
hooked. This applies only to LP8733.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This makes the initial changes need to support the
a38x series of SOCs. It adds the device-tree identifier
as well as changing the board_support function to take
the IO address designated by device-tree.
Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use fdt_addr_t; update 37xx and 8K implementations]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
After updating u-boot from v2016.01 to 2017.09, issue with
"SATA link 0 timeout." on my Cubietruck board.
mdelay milled after moving satapwr code to board.
"sunxi: Turn satapwr on from board_init"
(sha1: 9fbb0c3aa4)
After adding the "mdelay(500);"
line that was lost in the path the error is gone.
Signed-off-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de>
[Rebased and updated change and commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
As part of my usual round of build testing, output about missing
MAINTAINERS information was not logged, and thus often overlooked.
Correct that mistake by ensuring that I log the output of
genboardscfg.py every time. As part of that, address a number of
missing MAINTAINERS entires. In the case of a missing file, I have put
the original submitter down. In the rest of the cases I have added the
config (and sometimes relevant header file) to the existing set of file
globs.
Signed-off-by: Tom Rini <trini@konsulko.com>
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.
This also brings the benefit to allowing setup_sata() to be called for the
mx6qp wandboard variant.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Enable UMS and DFU, so that the eMMC can be accessed via the
USB gadget port on the board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Since DM_USB enabled, no need the usb code in board file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Add support for the latest MX6QP wandboard variant.
Based on Richard Hu's work from Technexion's U-Boot tree.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.
These change where introduced in phy driver in commit 05b29aa0cb
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This comment creates a wrong entry in config_whitelist.txt.
I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We add the various SMC91XX symbols to drivers/net/Kconfig and then this
converts the following to Kconfig:
CONFIG_SMC911X
CONFIG_SMC911X_BASE
CONFIG_SMC911X_16_BIT
CONFIG_SMC911X_32_BIT
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Apply to the rest of the tree, re-squash old and new patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.
So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Last user of this option went away in commit:
fdc7718999 ("board: usb_a9263: Update to support DT and DM")
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Add support for the DHCOM i.MX6 PDK board. This board has:
- FEC ethernet
- EHCI USB host
- 3x SDMMC
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
UART pinmux has been changed on the last board revision. Change
board pinmux accordingly. Console is on UART7 now, add pinmux,
base address and update console string in environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Latest wandboard hardware revision is revd1, which brings the following
new features:
- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.
The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.
As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.
Make the necessary adjustments for the AR8035 PHY to work on revd1.
Based on Richard Hu's work from Technexion's U-Boot tree.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Instead of changing mmc devno from dts nodes better
to return the detected devno so-that env trigger the same.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
When compiling with W=1 the following warning is observed:
board/freescale/mx6sabresd/mx6sabresd.c:586:5: warning: no previous prototype for ‘board_ehci_hcd_init’ [-Wmissing-prototypes] int board_ehci_hcd_init(int port)
Remove this warning by including <usb/ehci-ci.h>.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
When compiling with W=1 the following warning is observed:
board/freescale/mx6sabresd/mx6sabresd.c:680:5: warning: no previous prototype for ‘board_spi_cs_gpio’ [-Wmissing-prototypes] int board_spi_cs_gpio(unsigned bus, unsigned cs)
Remove this warning by including <asm/mach-imx/spi.h>.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
When building with W=1 errors like the one below is seen:
board/freescale/mx6sabresd/mx6sabresd.c:546:5: warning:
no previous prototype for ‘overwrite_console’
[-Wmissing-prototypes] int overwrite_console(void)
Fix the build warnings by including <input.h>.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
There is no need call setup_display() from SPL code, so move it to
board_init(), which executes only in U-Boot proper.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The ULCB CPLD support was not updated during the PFC table rework,
fix up the GPIO numbers until the CPLD support is rewritten to a
proper DM capable and DT probing driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.
Signed-off-by: York Sun <york.sun@nxp.com>
