Add device tree for T1042D4RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.
This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versa
This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.
Update rootfs start address to reflect correct memory map.
Also fix minor typo in README
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.
So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.
T1042RDB_PI is similar to T1040RDB board with few differences like
it has video interface, supports T1042 personality
T1042RDB_PI board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Two on-board RGMII 10/100/1G ethernet ports.
- SERDES Connections, 8 lanes supporting:
— PCI
— SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Video
- DIU supports video at up to 1280x1024x32bpp
- HDMI connector
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Device connected: EEPROM, thermal monitor, VID controller, RTC
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
