Now that we have falcon mode enabled, the partiton numbers for NAND have
changed, and we need to list entries for updating these parts of the
system. While adding falcon mode entires for eMMC (raw), we round up
the limit on U-Boot for ease of math later.
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz
used by OMAP34xx/OMAP35xx.
Also fix checkpatch warning about alignment.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Currently, we assume that if we can read from MMC correctly, we have
found a valid image. This is not the case as an empty area will read
just fine. Add a check for a valid IH_MAGIC.
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
The current code uses clrbits_be32 which is incorrect since we are on
a little endian machine here. This patch fixes this issue and also removes
some unnecessary code: Reading the current GPIO bank state is not required
if we are using the SET and CLEAR GPIO registers for setting/clearing
bits.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.
Conflicts:
arch/mips/cpu/mips64/start.S
Signed-off-by: Tom Rini <trini@ti.com>
Because the SOCFPGA platform will include support for Cyclone V and
Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to
be more generic.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>
v2:
- Add Reviewed-by: Pavel Machek
- Cc: Tom Rini
Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
Restrict autoboot interruption to "s" or "d" keys. This will prevent some
unwanted stopping and also allow disabling the reset on command timeout.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Accessing powered down peripherals will hang the bus, so check power
domain status before initializing SATA and fixup the FDT to disable
unused peripherals.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The timer_init function is called before relocation and writes to bss data
were corrupting relocation data. Fix this by removing the call to
reset_timer_masked. The initial timer count should be 0 or near 0 anyway,
so initializing the variables are not needed.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Various changes to highbank config:
Enable EFI partitions
Enable ext4 and FAT filesystems
Enable bootz command and raw initrd
Increase cmd and print buffer size to 1K
Change serial baudrate to 115200
Enable hush shell
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
There is no reason to wait for the entire frame to start DMA on receive,
so enable rx cut-thru for better performance.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
interrupt_init also sets up the abort stack, but is not setup before
relocation. So any aborts during relocation will hang and not print out
any useful information. Fix this by moving the interrupt_init to after
the stack setup in board_init_f.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Make it similar to the code in mips64/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Synchronize the code with mips64/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.
Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
The MIPS code uses centralized u-boot.lds script already,
and dynamic relocation is supported as well.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Checking mips32/time.c with checkpatch.pl shows this:
arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters
arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required
total: 1 errors, 1 warnings, 0 checks, 85 lines checked
Fix the code to make checkpatch.pl happy.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Qemu emulates a PCNET PCI card for the Malta CoreLV board.
Enable the pcnet driver and add board specific ethernet
initialization function to bring it up. Also enable the
CONFIG_CMD_NET and CONFIG_CMD_PING options.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.
The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Move the GT64120 register base to 0x1be00000
and setup PCI BAR registers as done by the
original YAMON bootloader.
This is needed for running Linux kernel.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The MIPS Malta board has a SOFTRES register. Writing a
magic value into that register initiates a board reset.
Use this feature to implement reset support.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.
This is enough to boot U-Boot to the command prompt
both in little and big endian mode.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.
This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The Linux specific register access macros, the
extern function declarations and the UL suffixes
has been removed.
The header file will be used for the qemu-malta
board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.
On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.
Conflicts:
board/sandburst/common/ppc440gx_i2c.c
board/sandburst/common/ppc440gx_i2c.h
Signed-off-by: Tom Rini <trini@ti.com>
