Commit graph

1251 commits

Author SHA1 Message Date
Roger Knecht
23c0df6e7c cmd: xxd: add new command
Add xxd command to print file content as hexdump to standard out

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Roger Knecht <rknecht@pm.me>
2022-10-11 15:40:48 -04:00
Roger Knecht
690a1d6948 cmd: cat: add new command
Add cat command to print file content to standard out

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Roger Knecht <rknecht@pm.me>
2022-10-11 15:40:48 -04:00
Tom Rini
300077cf8c Xilinx changes for v2023.01-rc1 (round 3)
fpga:
 - Create new uclass
 - Get rid of FPGA_DEBUG and use logging infrastructure
 
 zynq:
 - Enable early EEPROM decoding
 - Some DT updates
 
 zynqmp:
 - Use OCM_BANK_0 to check config loading permission
 - Change config object loading in SPL
 - Some DT updates
 
 net:
 - emaclite: Enable driver for RISC-V
 
 xilinx:
 - Fix static checker warnings
 - Fix GCC12 warning
 
 sdhci:
 - Read PD id from DT
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Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT
2022-10-11 09:57:08 -04:00
Ilias Apalodimas
1af680d5bc MAINTAINERS: get rid of the optee variables entry
Since I am co-maintaining EFI with Heinrich remove the special
entry for EFI variable storage via OP-TEE

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-10-06 22:54:58 +02:00
Alexander Dahl
1323d08bdf dm: fpga: Introduce new uclass
For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.

Suggested-by: Michal Simek <michal.simek@amd.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Dahl <post@lespocky.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 08:43:53 +02:00
Tom Rini
55ccdee315 Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
 - Add support for new Versal NET SOC
 
 zynqmp:
 - Use mdio bus for ethernet phy description
 - Wire ethernet phy reset via i2c-gpio
 
 versal:
 - Config cleanup
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Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.01-rc1 (round 2)

xilinx:
- Add support for new Versal NET SOC

zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio

versal:
- Config cleanup
2022-09-26 11:28:14 -04:00
Michal Simek
f6aebdf676 arm64: versal-net: Add support for Versal NET platform
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Weijie Gao
812f3c4e0a MAINTAINERS: update maintainer for MediaTek ARM platform
Add new files for MediaTek ARM platform

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:16 -04:00
Tom Rini
e9a1ff9724 Merge branch 'master' into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-19 16:07:12 -04:00
Fabio Estevam
b7d29fd8a7 MAINTAINERS: imx: Add an entry for the serial driver
Currently, when running ./scripts/get_maintainer.pl on serial_mxc.c
no i.MX maintainer is returned.

Fix it by adding an entry for this driver.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-09-18 22:56:10 +02:00
Jayesh Choudhary
29e1044741 configs: Add configs for j721s2 High Security EVM
Add j721s2 High Security EVM defconfig.

These configs are same as for the non-secure part, except for:
        CONFIG_TI_SECURE_DEVICE option set to 'y'
        CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
        CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
        CONFIG_BOOTCOMMAND uses FIT images for booting

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
2022-09-15 16:07:45 -04:00
Andrew Davis
360c7f46f3 configs: Add configs for J7200 High Security EVM
Add J7200 High Security EVM defconfig.

These defconfigs are the same as for the non-secure part, except for:
    CONFIG_TI_SECURE_DEVICE option set to 'y'
    CONFIG_BOOTCOMMAND uses FIT images for booting

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: add few configs from GP variant which were missing]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
2022-09-15 16:07:26 -04:00
Stefan Roese
1f865ee0ba cyclic: Add 'cyclic list' and 'cyclic demo' commands
This patch adds the cyclic command, which currently only supports the
'list' subcommand, to list all currently registered cyclic functions.
Here an example:

=> cyclic list
function: cyclic_demo, cpu-time: 7010 us, frequency: 99.80 times/s
function: cyclic_demo2, cpu-time: 1 us, frequency: 1.13 times/s

As you can see, the cpu-time is accounted, so that cyclic functions
that take too long might be discovered. Additionally the frequency is
logged.

The 'cyclic demo' commands registers the cyclic_demo() function to
be executed all 'cycletime_ms' milliseconds. The only thing this
function does is delaying by 'delay_us' microseconds.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-13 16:01:44 -04:00
Stefan Roese
c2c6971888 cyclic: Add basic support for cyclic function execution infrastruture
Add the basic infrastructure to periodically execute code, e.g. all
100ms. Examples for such functions might be LED blinking etc. The
functions that are hooked into this cyclic list should be small timewise
as otherwise the execution of the other code that relies on a high
frequent polling (e.g. UART rx char ready check) might be delayed too
much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.

How is this cyclic functionality executed?
The following patch integrates the main function responsible for
calling all registered cyclic functions cyclic_run() into the
common WATCHDOG_RESET macro. This guarantees that cyclic_run() is
executed very often, which is necessary for the cyclic functions to
get scheduled and executed at their configured periods.

This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-13 16:01:43 -04:00
Chin-Ting Kuo
4daa6bb6f7 spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.

There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
       fetches initial device boot image from FMC chip select(CS) 0.

- SPI1: Play the role of a SPI Master controller. Or, there is a
        dedicated path for HOST(X86) to access its BIOS flash mounted
        under BMC. spi-aspeed-smc.c implements the control sequence when
        SPI1 is a SPI master.

- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
        mounted under it are for pure storage purpose.

ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
               13h is used to fetch boot image from SPI flash.
               - AST2500: Only 03h command can be used after power on
                          or reset.
               - AST2600: If FMC04[6:4] is set, 13h command is used,
                          otherwise, 03h command.
               The address length is decided by FMC04[2:0].

- Command mode: SPI controller can send command and address
                automatically when CPU read/write the related remapped
                or decoded address area. The command used by this mode
                can be configured by FMC10/14/18[23:16]. Also, the
                address length is decided by FMC04[2:0]. This mode will
                be implemented in the following patch series.

- User mode: It is a traditional and pure SPI operation, where
             SPI transmission is controlled by CPU. It is the main
             mode in this patch.

Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.

This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13 12:08:40 -04:00
Neil Armstrong
23dc815c50 MAINTAINERS: Update email of Neil Armstrong
My professional e-mail will change and the BayLibre one will
bounce after mid-september of 2022.

This updates the MAINTAINERS files and adds an entry in the
.mailmap file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-08-20 16:17:50 -04:00
Gaurav Jain
47465877a5 ls1021atwr: caam: Enable Uboot validaion in SPL.
caam driver model enabled in spl for secure boot.
fsl_rsa_mod_exp driver enabled in spl for validating uboot image.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-08-16 17:07:30 +08:00
Joao Marcos Costa
468091a460 MAINTAINERS: Update e-mail address
Replace former professional address by my personal e-mail.

Signed-off-by: Joao Marcos Costa <jmcosta944@gmail.com>
2022-08-10 13:46:55 -04:00
Marek Behún
707b17f64e MAINTAINERS: Change POWERPC MPC85XX maintainer to Marek Behún
After a discussion with Tom Rini, we've agreed that I am going to take
over custodianship of the MPC85XX platform, since it seems other people
do not have necessary interest or time and getting things done over
there takes too long.

Since I am only working on one MPC85XX board, Turris 1.x, and do not
have time to do thorough reviews of patches for this entire platform
(other than those concerning Turris 1.x board), for other boards I will
only run patches through CI and checkpatch, and then send them via PR
upwards to Tom.

Signed-off-by: Marek Behún <kabel@kernel.org>
Acked-by: Tom Rini <trini@konsulko.com>
2022-08-01 10:08:43 -04:00
Tom Rini
86feeab3dc u-boot-imx-20220726
-------------------
 
 i.MX for 2022.10
 
 - Added i.MX93 architecture
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12891
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Merge tag 'u-boot-imx-20220726' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220726
-------------------

i.MX for 2022.10

- Added i.MX93 architecture

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12891
2022-07-26 10:26:00 -04:00
Martyn Welch
bb19f85168 MAINTAINERS: Update file list for ARM Freescale IMX
The MAINTAINERS file currently lists files in
arch/arm/include/asm/arch-imx/ being part of the IMX maintainers
purview, however the arch/arm/include/asm/ directory also contains the
directories arch-imx8, arch-imx8m, arch-imx8ulp and arch-imxrt which
would also appear to be relevant to the team. Tweak the entry to cover
these directories so that tools like get_maintainers.pl will suggest
relevant maintainers when making changes just in these directories.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-07-26 11:28:43 +02:00
Andrew Davis
86c4e533b0 defconfigs: Add a config for AM43xx HS EVM with QSPI Boot support
On AM43xx HS devices, QSPI boot is XIP and we use a single stage
bootloader. Add a defconfig for this.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-07-25 13:02:04 -04:00
Tom Rini
fd41c8f7a3 Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- octeontx_wdt: Add MIPS Octeon support (Stefan)
- watchdog: add amlogic watchdog support (Philippe)
- watchdog: add pulse support to gpio watchdog driver (Paul)
2022-07-22 20:48:28 -04:00
Marek Behún
61143f741e treewide: Fix Marek's name and change my e-mail address
Fix diacritics in some instances of my name and change my e-mail address
to kabel@kernel.org.

Add corresponding .mailmap entries.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Marek Behún
8a7880f0c1 board: turris: Fix MAINTAINERS and add Pali
Fix MAINTAINERS files for Turris devices, add missing files and add Pali
as maintainer.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Robert Marko
040978ae4f MAINTAINERS: add myself as Methode maintainer
I am currently maintaing the Methode uDPU and eDPU boards so add myself
as the maintainer for them.

Remove the old entry from board/Marvell/mvebu_armada-37xx/MAINTAINERS.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Philippe Boos
818055fd4e watchdog: add amlogic watchdog support
Add support for hardware watchdog timer for Amlogic SoCs.
This driver has been heavily inspired by his Linux equivalent
(meson_gxbb_wdt.c).

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Signed-off-by: Philippe Boos <pboos@baylibre.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 08:09:06 +02:00
Tom Rini
58f3dc5c4e - MIPS: add drivers and board support for Mediatek MT7621 SoC
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Merge tag 'mips-pull-2022-07-13' of https://source.denx.de/u-boot/custodians/u-boot-mips

- MIPS: add drivers and board support for Mediatek MT7621 SoC
2022-07-14 07:18:33 -04:00
Weijie Gao
dd6bf539e8 MAINTAINERS: update maintainer for MediaTek MIPS platform
Update maintainer for MediaTek MIPS platform

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-13 23:03:37 +02:00
Heinrich Schuchardt
a093d72e62 MAINTAINERS: add Ilias Apalodimas to EFI PAYLOAD as co-maintainer
Ilias has since long been reviewing UEFI patches.
Now he has volunteered to assist me in maintaining the sub-system.

Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-07-13 20:11:10 +02:00
Tom Rini
36b661dc91 Merge branch 'next' 2022-07-11 14:58:57 -04:00
Tom Rini
a457ebd786 arm: Remove PXA architecture support
With the last platform for this architecture removed, remove the rest of
the architecture support as well.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-07 09:29:08 -04:00
Michael Trimarchi
975918f6a1 MAINTAINERS: Add Dario and Michael as NAND maintainers
Both of us are working on NAND subsystem on several architectures and
we have boards and projects to improve the subsystem in uboot. The idea
is to guarantee quick feedback on patches sent on mailing list and most
of the time the possibilities to test them.

Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Tom Rini <trini@konsulko.com>
2022-07-01 16:00:54 -04:00
T Karthik Reddy
cf553bf20e arm64: versal: Add versal specific cadence ospi driver
Add support for cadence ospi driver for Versal platform. This driver
provides support for DMA read operation which utilizes cadence qspi
driver.
If "cdns,is-dma" DT property is specified use dma for read operation
from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in
cadence_ospi_versal driver add a weak function defination in
cadence_qspi driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 15:58:48 +02:00
Tom Rini
c316ee674f Xilinx changes for v2022.10
cpu:
 - Add driver for microblaze cpu
 
 net:
 - Add support for DM_ETH_PHY to AXI emac and emaclite
 
 xilinx:
 - Switch platforms to DM_ETH_PHY
 - DT chagnes in ZynqMP and Zynq
 - Enable support for SquashFS
 
 zynqmp:
 - Add support for KR260 boards
 - Move BSS from address 0
 - Move platform identification from board code to soc driver
 - Improve zynqmp_psu_init_minimize
 
 versal:
 - Enable loading app at EL1
 
 serial:
 - Setup default address and clock rates for DEBUG uarts
 
 pinctrl:
 - Add support for tri state and output enable properties
 
 relocate-rela:
 - Clean relocate-rela implementation for ARM64
 - Add support for Microblaze
 
 microblaze:
 - Add support for runtime relocation
 - Rework cache handling (wiring, Kconfig) based on cpuinfo
 - Remove interrupt support
 
 timer:
 - Extract axi timer driver from Microblaze to generic location
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
2022-06-27 10:15:50 -04:00
Michal Simek
a36d86720f microblaze: Convert axi timer to DM driver
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24 14:16:32 +02:00
Etienne Carriere
53355bb86c drivers: rng: add smccc trng driver
Adds random number generator driver using Arm SMCCC TRNG interface to
get entropy bytes from secure monitor. The driver registers as an
Arm SMCCC feature driver to allow PSCI driver to bind a device for
when secure monitor exposes RNG support from Arm SMCCC TRNG interface.

Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:56 -04:00
Janne Grunau
a30f60ca0b MAINTAINERS: Add nvme_apple to Apple SoC section
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Nick Hawkins
478c00718d MAINTAINERS: Introduce HPE GXP Architecture
Create a section in MAINTAINERS for the GXP HPE architecture

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:05 -04:00
Tom Rini
2f7821a927 - Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
 - Activate livetree for stm32mp15 DHSOM boards
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Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
2022-06-20 08:09:24 -04:00
Sean Anderson
2645bc0e12 arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:25 +08:00
Patrick Delaunay
b99293338e clk: Add directory for STM32 clock drivers
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I955af307963f732167396f0157a30cf2fc91f150
2022-06-17 14:11:43 +02:00
William Zhang
f8209d3051 arm: bcmbca: introduce the bcmbca architecture and 47622 SOC
This is the initial support for Broadcom's ARM-based 47622 SOC.

In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.

The SOC-specific code resides in arch/arm/mach-bcmbca/<soc> and board
related code is in board/broadcom/bcmba.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-06-10 13:37:32 -04:00
Sean Anderson
c8ce7ba87d misc: Add support for nvmem cells
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.

While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).

nvmem devices can specify "cells" in their device tree:

	qfprom: eeprom@700000 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x00700000 0x100000>;

		/* ... */

		tsens_calibration: calib@404 {
			reg = <0x404 0x10>;
		};
	};

which can then be referenced like:

	tsens {
		/* ... */
		nvmem-cells = <&tsens_calibration>;
		nvmem-cell-names = "calibration";
	};

The tsens driver could then read the calibration value like:

	struct nvmem_cell cal_cell;
	u8 cal[16];
	nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
	nvmem_cell_read(&cal_cell, cal, sizeof(cal));

Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.

Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.

The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-08 14:00:22 -04:00
Joel Stanley
24c8d1aba1 MAINTAINERS: aspeed: Add more files and myself as a reviewer
Add the rest of the ASPEED drivers that are in tree. Most are obvious,
except for ftgmac100 which matches the register layout used in the
ASPEED SoC.

I am the Linux maintainer for the ASPEED kernel port, and help maintain
the fork of u-boot used for OpenBMC, so add myself as a reviewer so I
can stay informed about u-boot changes.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-05-26 10:32:26 -04:00
Tom Rini
11232139e3 nds32: Remove the architecture
As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.

Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-04-25 16:04:05 -04:00
Tom Rini
8cfac237b9 Merge branch '2022-04-25-initial-implementation-of-stdboot'
To quote the author:
The bootflow feature provide a built-in way for U-Boot to automatically
boot an Operating System without custom scripting and other customisation.
This is called 'standard boot' since it provides a standard way for
U-Boot to boot a distro, without scripting.

It introduces the following concepts:

   - bootdev - a device which can hold a distro
   - bootmeth - a method to scan a bootdev to find bootflows (owned by
                U-Boot)
   - bootflow - a description of how to boot (owned by the distro)

This series provides an implementation of these, enabled to scan for
bootflows from MMC, USB and Ethernet. It supports the existing distro
boot as well as the EFI loader flow (bootefi/bootmgr). It works
similiarly to the existing script-based approach, but is native to
U-Boot.

With this we can boot on a Raspberry Pi 3 with just one command:

   bootflow scan -lb

which means to scan, listing (-l) each bootflow and trying to boot each
one (-b). The final patch shows this.

With a standard way to identify boot devices, booting become easier. It
also should be possible to support U-Boot scripts, for backwards
compatibility only.

...

The design is described in these two documents:

https://drive.google.com/file/d/1ggW0KJpUOR__vBkj3l61L2dav4ZkNC12/view?usp=sharing

https://drive.google.com/file/d/1kTrflO9vvGlKp-ZH_jlgb9TY3WYG6FF9/view?usp=sharing
2022-04-25 16:02:27 -04:00
Alper Nebi Yasak
06c73e37b3 MAINTAINERS: Add Alper as a binman maintainer
I ended up learning most of binman internals while trying to add a few
features to it, and I recently started reviewing binman series that
would not affect me personally. I'll keep working on it and try to do
more reviews.

Add myself as a maintainer for binman.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Acked-by: Tom Rini <trini@konsulko.com>
2022-04-25 10:11:05 -04:00
Simon Glass
e7b2ce191e bootstd: doc: Add documentation
Add documentation for this feature, including the commands and full
devicetree bindings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-25 10:00:04 -04:00
Simon Glass
fb1451bec2 bootstd: Add tests for bootstd including all uclasses
Add a set of combined tests for the bootdev, bootflow and bootmeth
commands, along with associated functionality.

Expand the sandbox console-recording limit so that these can work.

These tests rely on a filesystem script which is not yet added to the
Python tests. It is included here as a shell script.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-25 10:00:04 -04:00